MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 68

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.9.12.2.3
The timing is the same as the gated-clock mode (described in
except for the SENSB_HSYNC signal, which is not used. See
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
68
45.
SENSB_DATA[9:0]
SENSB_PIX_CLK
SENSB_DATA[7:0]
SENSB_HSYNC
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_VSYNC
Gated Clock Mode
Non-Gated Clock Mode
Start of Frame
Start of Frame
i.MX35 Applications Processors for Automotive Products, Rev. 9
invalid
invalid
Figure 46. Non-Gated Clock Mode Timing Diagram
nth frame
nth frame
Figure 45. Gated Clock Mode Timing Diagram
1st byte
1st byte
Active Line
n+1th frame
invalid
n+1th frame
Section 4.9.12.2.2, “Gated Clock
invalid
Figure
46. All incoming pixel clocks are
1st byte
1st byte
Freescale Semiconductor
Mode”),