MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 75

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.13.3
Functionality and electrical characteristics of the synchronous interface to dual-port smart displays are
identical to parameters of the synchronous interface. See
TFT LCD Panels, Electrical Characteristics.”
4.9.13.3.6
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The bits
D7–D0 of the value are mapped to bits LD17–LD10 of the data bus, respectively.
interface timing.
Freescale Semiconductor
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The frequency of the clock DISPB_D3_CLK is 27 MHz.
The DISPB_D3_HSYNC, DISPB_D3_VSYNC and DISPB_D3_DRDY signals are active low.
The transition to the next row is marked by the negative edge of the DISPB_D3_HSYNC signal.
It remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of the DISPB_D3_VSYNC
signal. It remains low for at least one clock cycle.
— At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC
— At a transition to an even field (of the same frame), they do not coincide.
The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC
signal being high.
and DISPB_D3_HSYNC coincide.
Synchronous Interface to Dual-Port Smart Displays
Interface to a TV Encoder—Functional Description
i.MX35 Applications Processors for Automotive Products, Rev. 9
Section 4.9.13.1.5, “Interface to Active Matrix
Figure 53
depicts the
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