MCIMX355AJQ5C Freescale Semiconductor, MCIMX355AJQ5C Datasheet - Page 57

• Manufacturer Part Number: MCIMX355AJQ5C
• Description: MULTIMEDIA PROCESSOR 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX355AJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX355
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, I2S, SPI, SSI, UART
• Maximum Clock Frequency: 133 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.22 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: IMX35PDK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.6
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator.
found in
Freescale Semiconductor
No.
73
62
63
64
65
66
67
68
69
70
71
72
74
75
78
79
Clock cycle
Clock high period
Clock low period
SCKR rising edge to FSR out (bl) high
SCKR rising edge to FSR out (bl) low
SCKR rising edge to FSR out (wr) high
SCKR rising edge to FSR out (wr) low
SCKR rising edge to FSR out (wl) high
SCKR rising edge to FSR out (wl) low
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
Data in hold time after SCKR falling edge
FSR input (bl, wr) high before SCKR falling edge
FSR input (wl) high before SCKR falling edge
FSR input hold time after SCKR falling edge
SCKT rising edge to FST out (bl) high
SCKT rising edge to FST out (bl) low
• For internal clock
• For external clock
• For internal clock
• For external clock
Figure 37
Table 43
Enhanced Serial Audio Interface (ESAI) Timing Specifications
4
and
shows the interface timing values. The number field in the table refers to timing signals
Characteristics
Figure
i.MX35 Applications Processors for Automotive Products, Rev. 9
Table 43. Enhanced Serial Audio Interface Timing
38.
1,2
5
5
5
Symbol
t
SSICC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Expression
2 × T c − 9.0
2 × T c − 9.0
4 × T c
4 × T c
2 × T c
2 × T c
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
Min.
30.0
30.0
12.0
19.0
12.0
12.0
3.5
9.0
2.0
2.0
2.5
8.5
15
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
Max. Condition
17.0
17.0
19.0
19.0
16.0
17.0
18.0
20.0
10.0
7.0
7.0
9.0
9.0
6.0
7.0
8.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
—
—
—
—
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
57