PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 103

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

13.2.3
The Capture overflow status flag bits are double
buffered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and
then the master bit is reset. The user can then read
TCONx to determine the value of CAxOVF.
EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS
TABLE 13-6:
Address
16h, Bank 3
17h, Bank 3
16h, Bank 7
12h, Bank 2
13h, Bank 2
16h, Bank 1
17h, Bank 1
10h, Bank 4
11h, Bank 4
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
16h, Bank 2
17h, Bank 2
14h, Bank 3
15h, Bank 3
12h, Bank 7
13h, Bank 7
14h, Bank 7
15h, Bank 7
Legend:
Note 1:
1997 Microchip Technology Inc.
MOVLB 3
MOVPF CA2L, LO_BYTE
MOVPF CA2H, HI_BYTE
MOVPF TCON2, STAT_VAL
READING THE CAPTURE REGISTERS
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition,
shaded cells are not used by Capture.
Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
Name
TCON1
TCON2
TCON3
TMR3L
TMR3H
PIR1
PIE1
PIR2
PIE2
PR3L/CA1L
PR3H/CA1H Timer3 period register, high byte/capture1 register, high byte
CA2L
CA2H
CA3L
CA3H
CA4L
CA4H
REGISTERS ASSOCIATED WITH CAPTURE
Holding register for the low byte of the 16-bit TMR3 register
Holding register for the high byte of the 16-bit TMR3 register
Timer3 period register, low byte/capture1 register, low byte
Capture2 low byte
Capture2 high byte
Capture3 low byte
Capture3 high byte
Capture4 low byte
Capture4 high byte
CA2ED1 CA2ED0
CA2OVF CA1OVF PWM2ON
SSPIE
SSPIF
RBIF
RBIE
PEIF
Bit 7
—
—
CA4OVF
TMR3IF
TMR3IE
T0CKIF
BCLIF
BCLIE
Bit 6
—
; Select Bank 3
; Read Capture2 low byte, store in LO_BYTE
; Read Capture2 high byte, store in HI_BYTE
; Read TCON2 into file STAT_VAL
CA1ED1
CA3OVF
TMR2IE
TMR2IF
STKAV
ADIF
ADIE
Bit 5
T0IF
Preliminary
PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000
CA1ED0
CA4ED1
TMR1IF
TMR1IE
GLINTD
Bit 4
INTF
—
—
CA4ED0 CA3ED1
CA2IF
CA2IE
CA4IF
CA4IE
PEIE
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, dif-
ferent registers will need to be read.
Bit 3
T16
TO
TMR3CS TMR2CS TMR1CS 0000 0000
T0CKIE
CA1IF
CA1IE
CA3IF
CA3IE
Bit 2
PD
CA3ED0 PWM3ON -000 0000
TX1IE
TX2IE
TX1IF
TX2IF
Bit 1
T0IE
POR
RC1IE
RC2IE
RC1IF
RC2IF
INTE
Bit 0
BOR
xxxx xxxx
xxxx xxxx
0000 0010
0000 0000
000- 0010
000- 0000
0000 0000
--11 1100
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
Value on
DS30264A-page 103
POR,
BOR
other resets
Value on all
0000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0000 0010
0000 0000
000- 0010
000- 0000
0000 0000
--11 qq11
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
(Note1)