PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 80

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

10.7
PORTG is an 8-bit wide bi-directional port. The corre-
sponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG
reads the status of the pins, whereas writing to them
will write to the respective port latch.
The lower four bits of PORTG are multiplexed with four
of the 12 channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
Upon reset the entire Port is automatically configured
as analog inputs, and must be configured in software
to be a digital I/O.
FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0
DS30264A-page 80
WR PORTG
WR DDRG
RD PORT
V
Data bus
AN
PORTG and DDRG Registers
PCFG3:PCFG0
CHS3:CHS0
Data Latch
DDRG Latch
D
CK
D
CK
RD DDRG
Q
Q
Q
Q
Q
Preliminary
EN
EN
D
To other pads
To other pads
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-7: INITIALIZING PORTG
MOVLB
MOVLW
MOVPF
CLRF
MOVLW
MOVWF
5
0x0E
ADCON1 ; digital
PORTG
0x03
DDRG
V
V
P
N
DD
SS
; Select Bank 5
; Configure PORTG as
; Initialize PORTG data
;
;
;
; Value used to initialize
;
; Set RG<1:0> as inputs
;
1997 Microchip Technology Inc.
latches before setting
the data direction
register
data direction
RG<7:2> as outputs
ST
input
buffer
I/O pin