PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 135

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

15.2.1
In slave mode, the SCL and SDA pins must be config-
ured as inputs. The SSP module will override the input
state with the output data when required (slave-trans-
mitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR2<7>) is set.
Table 15-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I
the SSP module is shown in timing parameter #100
and parameter #101.
15.2.1.1
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
TABLE 15-2:
1997 Microchip Technology Inc.
Transfer is Received
Status Bits as Data
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON1<6>) was
set before the transfer was received.
BF
0
1
1
0
2
C specification as well as the requirement of
SLAVE MODE
ADDRESSING
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
SSPSR
Yes
No
No
No
SSPBUF
Preliminary
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Generate ACK
Note:
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR2<7>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address, if match occurs releases the
SCL line, this will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Pulse
Yes
No
No
No
Following the RESTART condition (step 7)
in 10-bit mode, the user only needs to
match the first 7-bit address. The user
does not update the SSPADD for the sec-
ond half of the address.
(SSP Interrupt occurs
Set bit SSPIF
if enabled)
DS30264A-page 135
Yes
Yes
Yes
Yes