PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 193

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

CALL
Syntax:
Operands:
Operation:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Status Affected:
Encoding:
1997 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
PC =
PC =
TOS =
Q1
No
Read literal
Push PC to
Address(HERE)
Address(THERE)
Address (HERE + 1)
operation
Subroutine Call
[ label ] CALL k
0
PC+ 1
k<12:8>
PC<15:13>
None
Subroutine call within 8K page. First,
return address (PC+1) is pushed onto
the stack. The 13-bit value is loaded
into PC bits<12:0>. Then the
upper-eight bits of the PC are copied
into PCLATH. CALL is a two-cycle
instruction.
See LCALL for calls outside 8K memory
space.
1
2
HERE
'k'<7:0>,
stack
111k
Q2
No
k
4095
TOS, k
kkkk
CALL
PCLATH<4:0>;
operation
Process
Data
PCLATH<7:5>
Q3
No
THERE
PC<12:0>,
kkkk
Write to PC
operation
Q4
No
kkkk
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register 'f'
Clear f
[ label ] CLRF
0
00h
00h
None
Clears the contents of the specified reg-
ister(s).
s = 0: Data memory location 'f' and
WREG are cleared.
s = 1: Data memory location 'f' is
cleared.
1
1
CLRF
Read
0010
Q2
=
=
f
255
f, s
dest
0x5A
0x00
100s
Process
[0,1]
FLAG_REG
Data
Q3
f,s
DS30264A-page 193
ffff
register 'f'
specified
WREG
and if
Write
Q4
ffff