PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 142

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

15.2.4
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. Control of the I
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP Interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check is performed in hardware, with the
result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Restart Condition
• An Acknowledge Condition
15.2.5
Master Mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting
the SSPEN bit. Once master mode is enabled, the
user has six options.
DS30264A-page 142
Note:
- Assert a start condition on SDA and SCL.
- Assert a restart condition on SDA and SCL.
- Write to the SSPBUF register initiating trans-
- Generate a stop Condition on SDA and SCL.
- Configure the I
- Generate an acknowledge condition at the end
mission of data/address.
of a received byte of data.
MULTI-MASTER MODE
I
2
C MASTER MODE SUPPORT
The SSP Module when configured in I
Master Mode does not allow queueing of
events.
allowed to intitiate a start condition, and
immediately write the SSPBUF register to
initate transmission before the START con-
dition is complete. In this case the SSP-
BUF will not be written to, and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur.
For instance: The user is not
2
C port to receive data.
Preliminary
2
2
C
C
15.2.5.1
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeated
START condition. Since the repeated START condi-
tion is also the beginning of the next serial transfer, the
I
In Master transmitter mode serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device, (7 bits) and the data direction bit. In
this case the data direction bit (R/W) will be logic '0'.
Serial data is transmitted 8 bits at a time. After each
byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the
beginning and the end of a serial transfer.
In Master receive mode the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the data direction bit. In this case the data
direction bit (R/W) will be logic '1'. Thus the first byte
transmitted is a 7-bit slave address followed by a '1' to
indicate receive bit. Serial data is received via SDA
while SCL outputs the serial clock.
received 8 bits at a time. After each byte is received,
an acknowledge bit is transmitted. START and STOP
conditions indicate the beginning and end of transmis-
sion.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz, or 1 MHz I
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.
transmission of the last data bit is followed by ACK)
the internal clock will automatically stop counting and
the SCL pin will remain in its last state
A typical transmit sequence would go as follows:
1.
2.
3.
4.
5.
6.
7.
8.
2
C bus will not be released.
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
start time before any other operation takes
place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The SSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of
data.
DATA is shifted out the SDA pin until all 8 bits
are transmitted.
I
2
C MASTER MODE OPERATION
1997 Microchip Technology Inc.
2
C operation. The baud
Serial data is