PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 46

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PIC17C756-33/L

Manufacturer Part Number
PIC17C756-33/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr

Specifications of PIC17C756-33/L

Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
TABLE 7-3:
DS30264A-page 46
Address
Bank 6:
10h
11h
12h
13h
14h
15h
16h
17h
Bank 7:
10h
11h
12h
13h
14h
15h
16h
17h
Legend:
Unbanked
Note 1:
18h
19h
(5)
(5)
2:
3:
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Name
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
PW3DCL
PW3DCH
CA3L
CA3H
CA4L
CA4H
TCON3
PRODL
PRODH
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
SPECIAL FUNCTION REGISTERS (Cont.’d)
SSP Address register in I
Synchronous Serial Port Receive Buffer/Transmit Register
Capture3 low byte
Capture3 high byte
Capture4 low byte
Capture4 high byte
Low Byte of 16-bit Product (8 x 8 Hardware Multiply)
High Byte of 16-bit Product (8 x 8 Hardware Multiply)
WCOL
GCEN
Bit 7
SMP
DC1
DC9
CA4OVF
AKSTAT
SSPOV
Bit 6
CKE
DC0
DC8
TM2PW3
CA3OVF
SSPEN
AKDT
Bit 5
DC7
2
D/A
C slave mode. SSP baud rate reload register in I
CA4ED1
AKEN
Preliminary
Bit 4
CKP
DC6
P
-
CA4ED0
SSPM3
RCEN
Bit 3
DC5
S
-
CA3ED1
SSPM2
Bit 2
PEN
R/W
DC4
-
CA3ED0
SSPM1
RSEN
Bit 1
DC3
2
UA
C master mode.
-
PWM3ON -000 0000 -000 0000
SSPM0
1997 Microchip Technology Inc.
Bit 0
SEN
DC2
BF
-
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
---- ---- ---- ----
---- ---- ---- ----
---- ---- ---- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- ---- ---- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
resets (3)
Value on
all other

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