PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 88

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

12.1
When the T0CS (T0STA<5>) bit is set, TMR0 incre-
ments on the internal clock. When T0CS is clear, TMR0
increments on the external clock (RA1/T0CKI pin). The
external clock edge can be selected in software. When
the T0SE (T0STA<6>) bit is set, the timer will increment
on the rising edge of the RA1/T0CKI pin. When T0SE
is clear, the timer will increment on the falling edge of
the RA1/T0CKI pin. The prescaler can be programmed
to introduce a prescale of 1:1 to 1:256. The timer incre-
ments from 0000h to FFFFh and rolls over to 0000h.
On overflow, the TMR0 Interrupt Flag bit (T0IF) is set.
The TMR0 interrupt can be masked by clearing the cor-
responding TMR0 Interrupt Enable bit (T0IE). The
TMR0 Interrupt Flag bit (T0IF) is automatically cleared
when vectoring to the TMR0 interrupt vector.
FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM
FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)
DS30264A-page 88
RA1/T0CKI
Timer0 Operation
(T0STA<6>)
T0SE
Increment
Prescaler
Prescaler
(PSOUT)
Sampled
output
output
TMR0
TMR0
Fosc/4
(T0STA<5>)
T0CS
Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
0
1
3: The PSOUT high time is too short and is missed by the sampling circuit.
2:
= PSOUT is sampled here.
T0PS3:T0PS0
(T0STA<4:1>)
(note 1)
Prescaler
(8 stage
async ripple
counter)
T0
4
Preliminary
PSOUT
12.2
When an external clock input is used for Timer0, it is
synchronized
Figure 12-3 shows the synchronization of the external
clock. This synchronization is done after the prescaler.
The output of the prescaler (PSOUT) is sampled twice
in every instruction cycle to detect a rising or a falling
edge. The timing requirements for the external clock
are detailed in the electrical specification section.
12.2.1
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time TMR0 is actually
incremented. Figure 12-3 shows that this delay is
between 3T
suring the interval between two edges (e.g. period) will
be accurate within 4T
Synchronization
Q2
T0 + 1
Using Timer0 with External Clock
DELAY FROM EXTERNAL CLOCK EDGE
OSC
Q4
with
and 7T
TMR0H<8> TMR0L<8>
the
OSC
(note 3)
OSC
1997 Microchip Technology Inc.
T0 + 2
( 121 ns @ 33 MHz).
. Thus, for example, mea-
internal
(note 2)
Interrupt on overflow
(INTSTA<5>)
sets T0IF
phase
clocks.