PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 159

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PIC17C756-33/L

Manufacturer Part Number
PIC17C756-33/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr

Specifications of PIC17C756-33/L

Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
15.2.13 CLOCK ARBITRATION
Clock arbitration occurs when the master during any
receive, transmit, or restart/stop condition de-asserts
the SCL pin (SCL allowed to float high).
SCL pin is allowed to float high, the baud rate genera-
tor (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the
clock is held low by an external device. (Figure 15-36)
FIGURE 15-36: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
1997 Microchip Technology Inc.
SCL
SDA
T
BRG
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
When the
T
BRG
Preliminary
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
T
SCL = 1 BRG starts counting
clock high interval.
BRG
osc
DS30264A-page 159
4).

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