PIC17C756-33/L Microchip Technology, PIC17C756-33/L Datasheet - Page 53

• Manufacturer Part Number: PIC17C756-33/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

7.8
The BSR is used to switch between banks in the data
memory area (Figure 7-12). In the PIC17C752, and
PIC17C756 devices, the entire byte is implemented.
The lower nibble is used to select the peripheral regis-
ter bank. The upper nibble is used to select the general
purpose memory bank.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank
to bank in order to address all peripherals related to a
single task. To assist this, a MOVLB bank instruction
has been included in the instruction set.
FIGURE 7-12: BSR OPERATION
Note 1:
Address
Range
1997 Microchip Technology Inc.
10h
17h
20h
FFh
2: Bank 0 and Bank 1 are implemented for the PIC17C752, and Banks 0 through 3 are implemented for the PIC17C756.
BSR
7
Bank Select Register (BSR)
Only Banks 0 through 7 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
Selection of an unimplemented bank is not recommended.
(2)
4 3
Bank 0
(1)
0
Bank 0
0
0
Bank 1
1
Bank 1
Bank 2
1
2
Bank 3
3
Bank 2
2
Bank 4
4
Preliminary
Bank 3
Bank 5
3
5
Bank 6
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank instruction has been provided in the instruction
set.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
Bank 4
6
Note:
4
Bank 7
7
Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
Bank 8
8
Bank 15
Bank 15
15
15
SFR
Banks
GPR
Banks
DS30264A-page 53
(Peripheral)
(RAM)