MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 111

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.3.2
After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the RAMBAR
is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the
following steps should be performed:
The ColdFire processor or an external emulator using the debug module can perform these initialization
functions.
5.3.3
The following code segment describes how to initialize the SRAM. The code sets the base address of the
SRAM at 0x20000000 and then initializes the SRAM to zeros.
RAMBASE
RAMVALID
move.l
movec.l
Freescale Semiconductor
1. Load the RAMBAR mapping the SRAM module to the desired location within the address space.
2. Read the source data and write it to the SRAM. There are various instructions to support this
3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into
Bits
5–1
0
function, including memory-to-memory move instructions, or the MOVEM opcode. The
MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses,
so this opcode generally provides maximum performance.
the RAMBAR with a new set of attributes. These attributes consist of the write-protect and
address space mask fields.
SRAM Initialization
SRAM Initialization Code
C/I, SC, SD,
UC, UD
Name
V
EQU $20000000
EQU $00000001
#RAMBASE+RAMVALID,D0
D0, RAMBAR
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 5-1. SRAM Base Address Register (continued)
Address space masks (ASn)
These five bit fields allow certain types of accesses to be “masked,” or inhibited from
accessing the SRAM module. The address space mask bits are:
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
These bits are useful for power management as detailed in
Management.”
Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module;
otherwise, the module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
space is made, it is inhibited from accessing the SRAM module, and is processed like
any other non-SRAM reference.
;set this variable to $20000000
;load RAMBASE + valid bit into D0.
;load RAMBAR and enable SRAM
Description
Section 5.3.4, “Power
Static RAM (SRAM)
5-3