MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 665

IC MPU 32BIT COLDF 256-MAPBGA

MCF5280CVM66

Manufacturer Part Number
MCF5280CVM66
Description
IC MPU 32BIT COLDF 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5280CVM66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
No. Of I/o's
150
Program Memory Size
2KB
Ram Memory Size
64KB
Cpu Speed
66.67MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Chapter 31
IEEE 1149.1 Test Access Port (JTAG)
The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the
IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing
testing.
This architecture provides access to all data and chip control pins from the board-edge connector through
the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
Figure 31-1
Freescale Semiconductor
TRST/DSCLK
TMS/BKPT
JTAG_EN
TDI/DSI
TCLK
shows the block diagram of the JTAG module.
JTAG Module
147
31
6
2
3
148-BIT BOUNDARY SCAN REGISTER
7-BIT JTAG_CFM_CLKDIV REGISTER
4-BIT TAP INSTRUCTION DECODER
4-BIT TAP INSTRUCTION REGISTER
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
1-BIT BYPASS REGISTER
3-BIT TEST_CTRL REGISTER
32-BIT IDCODE REGISTER
TAP CONTROLLER
Figure 31-1. JTAG Block Diagram
to Debug Module
Disable DSCLK
Force BKPT = 1
0
0
0
0
0
DSI
= 0
DSO
DSI
BKPT
DSCLK
0
1
1
0
TDO/DSO
31-1

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