MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 274

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Synchronous DRAM Controller Module
The DRAM controller’s major components are as follows:
15-2
•
•
•
•
•
Internal
Q[31:0] internal
A[23:0]
D[31:0] internal
Bus
DRAM address and control registers (DACR0 and DACR1)—The DRAM controller consists of
two configuration register units, one for each supported memory block. DACR0 is accessed at
IPSBAR + 0x048; DACR1 is accessed at IPSBAR + 0x050. The register information is passed on
to the hit logic.
Control logic and state machine—Generates all SDRAM signals, taking hit information and
bus-cycle characteristic data from the block logic in order to generate SDRAM accesses. Handles
refresh requests from the refresh counter.
— DRAM control register (DCR)—Contains data to control refresh operation of the DRAM
— Refresh counter—Determines when refresh should occur; controlled by the value of DCR[RC].
Hit logic—Compares address and attribute signals of a current SDRAM bus cycle to both DACRs
to determine if an SDRAM block is being accessed. Hits are passed to the control logic along with
characteristics of the bus cycle to be generated.
Address multiplexing—Multiplexes addresses to allow column and row addresses to share pins.
This allows glueless interface to SDRAMs.
Data Generation—Controls the data input and data output transmission between the on-platform
and off-platform data buses.
controller. Both memory blocks are refreshed concurrently as controlled by DCR[RC].
It generates a refresh request to the control block.
DRAM Controller Module
DRAM Address/Control Register 0
DRAM Address/Control Register 1
Memory Block 0 Hit Logic
Memory Block 1 Hit Logic
Figure 15-1. Synchronous DRAM Controller Block Diagram
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
(DACR0)
(DACR1)
Refresh Counter
Register (DCR)
DRAM Control
State Machine
Control Logic
Multiplexing
Generation
Address
Data
and
D[31:0]
A[23:0]
D[31:0]
SDRAM_CS[1:0]
SCAS
SRAS
SCKE
DRAMW
BS[3:0]
Freescale Semiconductor