MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 439

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

UART Modules
optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the
transmitter output on the falling edge of the clock source.
After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output
remains high (mark condition) and the transmitter empty bit (USRn[TXEMP]) is set. Transmission
resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer
(UTBn). If the transmitter receives a disable command, it continues until any character in the transmitter
shift register is completely sent.
If the transmitter is reset through a software command, operation stops immediately (see
Section 23.3.5,
“UART Command Registers
(UCRn)”). The transmitter is reenabled through the UCRn to resume
operation after a disable or software reset.
If the clear-to-send operation is enabled, UCTSn must be asserted for the character to be transmitted. If
UCTSn is negated in the middle of a transmission, the character in the shift register is sent and UTXDn
remains in mark state until UCTSn is reasserted. If transmitter is forced to send a continuous low condition
by issuing a
command, transmitter ignores the state of UCTSn.
SEND BREAK
If the transmitter is programmed to automatically negate URTSn when a message transmission completes,
URTSn must be asserted manually before a message is sent. In applications in which the transmitter is
disabled after transmission is complete and URTSn is appropriately programmed, URTSn is negated one
bit time after the character in the shift register is completely transmitted. The transmitter must be manually
reenabled by reasserting URTSn before the next message is sent.
Figure 23-19
shows the functional timing information for the transmitter.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
23-19