MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 99

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Chapter 4
Cache
4.1
This chapter describes cache operation on the ColdFire processor.
4.1.1
Features include the following:
4.1.2
The cache is a direct-mapped, single-cycle memory. It may be configured as an instruction cache, a
write-through data cache, or a split instruction/data cache. The cache storage is organized as
each containing 16 bytes. The memory storage consists of a
a valid bit), and a data array containing
Cache configuration is controlled by bits in the cache control register (CACR), detailed later in this
chapter. For the instruction or data-only configurations, only the associated instruction or data line-fill
buffer is used. For the split cache configuration, one-half of the tag and storage arrays is used for an
instruction cache and one-half is used for a data cache. The split cache configuration uses the instruction
and the data line-fill buffers. The core’s local bus is a unified bus used for instruction and data fetches.
Therefore, the cache can have only one fetch, instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are accessed in parallel:
fetch address bits [
For the split cache configuration, the cache tag and storage arrays are accessed in parallel. The msb of the
tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [
provide the rest of the tag array address. The tag array outputs the address mapped to the given cache
location along with the valid bit for the line. This address field is compared to bits [31:
or data-only configurations and to bits [31:
bus to determine if a cache hit has occurred. If the desired address is mapped into the cache memory, the
Freescale Semiconductor
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Configurable as instruction, data, or split instruction/data cache
2
Single-cycle access on cache hits
Physically located on the ColdFire core's high-speed local bus
Nonblocking design to maximize performance
Separate instruction and data 16-Byte line-fill buffers
Configurable instruction cache miss-fetch algorithm
-Kbyte direct-mapped cache
Introduction
Features
Introduction
10
:4] addressing the tag array, and fetch address bits [
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
2
Kbytes, organized as
10
] for a split configuration of the fetch address from the local
128
512
-entry tag array (containing addresses and
× 32 bits.
10
:2] addressing the storage array.
11
] for instruction-
128
9
lines,
:4]
4-1