PIC16F690-E/ML Microchip Technology, PIC16F690-E/ML Datasheet - Page 148

• Manufacturer Part Number: PIC16F690-E/ML
• Description: IC, 8BIT MCU, PIC16F, 20MHZ, QFN-20
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F690-E/ML

• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 4096 Words
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20QFN-1 - SOCKET TRANSITION 20DIP-20QFNAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
11.4.7
In Single Output mode, pulse steering allows any of the
PWM pins to be the modulated signal. Additionally, the
same PWM signal can be simultaneously available on
multiple pins.
Once
(CCP1M<3:2> = 11
CCP1CON register), the user firmware can bring out
the same PWM signal to one, two, three or four output
pins by setting the appropriate STR<D:A> bits of the
PSTRCON register, as shown in Figure 11-19.
REGISTER 11-4:
DS41262E-page 146
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
the
The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and
P1M<1:0> = 00.
PULSE STEERING MODE
Single
Unimplemented: Read as ‘0’
STRSYNC: Steering Sync bit
1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary
STRD: Steering Enable bit D
1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1D pin is assigned to port pin
STRC: Steering Enable bit C
1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1C pin is assigned to port pin
STRB: Steering Enable bit B
1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1B pin is assigned to port pin
STRA: Steering Enable bit A
1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0>
0 = P1A pin is assigned to port pin
U-0
—
and
PSTRCON: PULSE STEERING CONTROL REGISTER
Output
P1M<1:0> = 00
W = Writable bit
‘1’ = Bit is set
mode
U-0
—
is
selected
STRSYNC
of
R/W-0
the
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
STRD
While the PWM Steering mode is active, CCP1M<1:0>
bits of the CCP1CON register select the PWM output
polarity for the P1<D:A> pins.
The PWM auto-shutdown operation also applies to
PWM Steering mode as described in Section 11.4.4
“Enhanced
auto-shutdown event will only affect pins that have
PWM outputs enabled.
Note:
The associated TRIS bits must be set to
output (‘0’) to enable the pin output driver
in order to see the PWM signal on the pin.
PWM
R/W-0
STRC
(1)
Auto-shutdown
© 2008 Microchip Technology Inc.
x = Bit is unknown
R/W-0
STRB
mode”.
R/W-1
STRA
bit 0
An