PIC16F690-E/ML Microchip Technology, PIC16F690-E/ML Datasheet - Page 190

• Manufacturer Part Number: PIC16F690-E/ML
• Description: IC, 8BIT MCU, PIC16F, 20MHZ, QFN-20
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F690-E/ML

• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 4096 Words
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20QFN-1 - SOCKET TRANSITION 20DIP-20QFNAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

specifications, as well as 7-bit and 10-bit addressing.
PIC16F631/677/685/687/689/690
13.11 SSP I
The SSP module in I
functions, except general call support, and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
Two pins are used for data transfer. These are the RB6/
SCK/SCL pin, which is the clock (SCL), and the RB4/
AN10/SDI/SDA pin, which is the data (SDA).
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 13-7:
The SSP module has six registers for the I
which are listed below.
• SSP Control register (SSPCON)
• SSP Status register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift register (SSPSR) – Not directly
• SSP Address register (SSPADD)
• SSP Mask register (SSPMSK)
DS41262E-page 188
SDI/SDA
AN10/
SCK/
RB4/
accessible
RB6/
SCL
module
Read
Clock
2
Shift
implements
C Operation
MSb
2
C mode, fully implements all slave
SSP BLOCK DIAGRAM
(I
Stop bit Detect
SSPMSK Reg
SSPADD Reg
SSPBUF Reg
Match Detect
SSPSR Reg
2
Start and
C™ MODE)
the
LSb
Standard
Write
(SSPSTAT Reg)
Internal
Data Bus
2
Set, Reset
S, P bits
C operation,
Addr Match
mode
The SSPCON register allows control of the I
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I
13.12 Slave Mode
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISB<6,4> are set). The SSP
module will override the input state with the output data
when required (slave-transmitter).
When an address is matched, or the data transfer after
an address match
automatically will generate the Acknowledge (ACK)
pulse, and then load the SSPBUF register with the
received value currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
b)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF of the PIR1 register is
set. Table 13-3 shows the results of when a data
transfer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow
condition. Flag bit BF is cleared by reading the
SSPBUF register, while bit SSPOV is cleared through
software.
The SCL clock input must have a minimum high and low
for proper operation. For high and low times of the I
specification, as well as the requirements of the SSP
module, see Section 17.0 “Electrical Specifications”.
Stop bit interrupts enabled to support Firmware
Master mode
Stop bit interrupts enabled to support Firmware
Master mode
support Firmware Master mode; Slave is idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with Start and
C Slave mode (10-bit address), with Start and
C Start and Stop bit interrupts enabled to
The Buffer Full bit BF of the SSPSTAT register
was set before the transfer was received.
The overflow bit SSPOV of the SSPCON
register was set before the transfer was
received.
2
C mode with the SSPEN bit set
is received,
© 2008 Microchip Technology Inc.
2
C modes to be selected:
2
C module.
the
hardware
2
2
C
C