PIC16F690-E/ML Microchip Technology, PIC16F690-E/ML Datasheet - Page 96

• Manufacturer Part Number: PIC16F690-E/ML
• Description: IC, 8BIT MCU, PIC16F, 20MHZ, QFN-20
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F690-E/ML

• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 4096 Words
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20QFN-1 - SOCKET TRANSITION 20DIP-20QFNAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F631/677/685/687/689/690
FIGURE 8-2:
FIGURE 8-3:
DS41262E-page 94
FixedRef
CV
C2V
FixedRef
CV
C1V
REF
REF
REN
REN
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C2CH<1:0>
C2IN+
C1IN+
0
1
C1CH<1:0>
MUX
0
1
MUX
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C2R
C1R
0
1
2
3
0
1
2
MUX
MUX
0
1
2
3
0
1
Note 1:
2
MUX
MUX
Note 1:
2:
3:
2:
3:
C2V
C2V
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C1V
C1V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
IN
IN
-
+
IN
IN
-
+
C2
C2ON
+
-
C1
C1ON
C2POL
(1)
C1POL
(1)
From TMR1
Q3*RD_CM2CON0
Clock
Q3*RD_CM1CON0
Q1
Q1
D
NRESET
C2OUT
D
EN
NRESET
D
EN
C1OUT
Q
Q
C2SYNC
Q
D
EN
C2POL
D
EN
CL
C1POL
0
1
MUX
CL
Q
Q
© 2008 Microchip Technology Inc.
to Timer1 Gate, SR latch
and other peripherals
To other peripherals
C1OUT (to SR latch)
OSC
RD_CM2CON0
OSC
RD_CM1CON0
).
).
SYNCC2OUT
Data Bus
Set C2IF
Data Bus
Set C1IF
To
To