PIC16F690-E/ML Microchip Technology, PIC16F690-E/ML Datasheet - Page 211

• Manufacturer Part Number: PIC16F690-E/ML
• Description: IC, 8BIT MCU, PIC16F, 20MHZ, QFN-20
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F690-E/ML

• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Core Size: 8 Bit
• Program Memory Size: 4096 Words
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20QFN-1 - SOCKET TRANSITION 20DIP-20QFNAC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNPIC16F690DM-PCTLHS - BOARD DEMO PICTAIL HUMIDITY SNSRAC162061 - HEADER INTRFC MPLAB ICD2 20PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

14.3.2
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
FIGURE 14-7:
© 2008 Microchip Technology Inc.
IOC-RA0
IOC-RA1
IOC-RA2
IOC-RA3
IOC-RA4
IOC-RA5
IOC-RB4
IOC-RB5
IOC-RB6
IOC-RB7
IOCA0
IOCA1
IOCA2
IOCA3
IOCA4
IOCA5
IOCB4
IOCB5
IOCB6
IOCB7
TIMER0 INTERRUPT
INTERRUPT LOGIC
PIC16F631/677/685/687/689/690
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP1IF
CCP1IE
SSPIF
SSPIE
OSFIF
OSFIE
RCIF
RCIE
ADIF
ADIE
EEIE
TXIF
TXIE
C1IF
C1IE
C2IF
C2IE
EEIF
14.3.3
An input change on PORTA or PORTB change sets the
RABIF (INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RABIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA or IOCB registers.
Note 1:
Note:
RABIF
RABIE
INTF
INTE
PEIE
T0IF
T0IE
GIE
PORTA/PORTB INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. See
Section 4.2.3 “Interrupt-on-change” for
more information.
Some peripherals depend upon the system
clock for operation. Since the system clock is
suspended during Sleep, these peripherals
will not wake the part from Sleep. See
Section 14.6.1 “Wake-up from Sleep”.
Wake-up (If in Sleep mode)
DS41262E-page 209
Interrupt to CPU
(1)