EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 258

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

7
LUTSwCtrl
7-76
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
31
15
Address: 0x8003_0218
Default: 0x0000_0000
Definition: LUT Switching Control register
Bit Descriptions:
30
14
29
13
28
12
Where:
FRAME[1:0] = FRAME_CNT3 or FRAME_CNT4 as defined by FRAME at address Pixel_In
VCNT[1:0] = VERT_CNT3 or VERT_CNT4 as defined by VERT at address Pixel_In
HCNT[1:0] = HORZ_CNT3 or HORZ_CNT4 as defined by HORZ at address Pixel_In
RSVD:
SSTAT:
SWTCH:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Switch Status - Read Only
When SWTCH = ‘0’, Switch Status = ‘1’ means that RAM0
is in the video pipeline and RAM1 is accessible to the bus.
When SWTCH = ‘1’, Switch Status = ‘1’ means that RAM1
is in the video pipeline and RAM0 is accessible to the bus.
During active video, the switch does not occur until the
beginning of the next frame. When the video state
machine is disabled, the switch occurs almost
immediately.
Switch - Read/Write
Writing a Switch value to this bit selects which of these
conditions is present when SSTAT = ‘1’:
0 - RAM0 in video pipeline, RAM1 is accessible from bus
1 - RAM1 in video pipeline, RAM0 is accessible from bus.
RSVD
24
8
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
SSTAT
17
1
DS785UM1
SWTCH
16
0