EP9315-IBZ Cirrus Logic Inc, EP9315-IBZ Datasheet - Page 361

• Manufacturer Part Number: EP9315-IBZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-IBZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 65
• Package / Case: 352-PBGA
• Clock Frequency: 200MHz
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1263

DS785UM1
MOIE:
TxCOIE:
RxROIE:
MIIIE:
PHYSIE:
TIE:
SWIE:
TSQIE:
REOFIE, REOBIE, RHDRIE: Setting all three bits causes interrupts to be
Copyright 2007 Cirrus Logic
Receive Miss Overflow Interrupt Enable. If received
frames are lost due to slow movement of receive data out
of the receive buffers, then a receive miss is said to have
occurred. When this happens, the RxMISS counter is
incremented. When the MSB of the count is set, the
MissCnt bit in the Interrupt Status Register is set. If the
MissCntiE bit is set at this time, an interrupt is generated.
Transmit Collision Overflow Interrupt Enable. When a
transmit collision occurs, the transmit collision count is
incremented. When the MSB of the count is set, the
TXCollCnt bit in the Interrupt Status Register is set. If the
TxCollCntiE is set at this time, an interrupt is generated.
Receive Runt Overflow Interrupt Enable. When a runt
frame is received with a CRC error, the RxRuntCnt register
is incremented. When the MSB of the count is set the
RuntOv bit is set in the Interrupt Status Register. If the
RuntOviE bit is set at this time, an interrupt is generated.
MII Management Interrupt Enable. When set, the MII
Interrupt enable causes an interrupt to be generated
whenever a management read or write cycle is completed
on the MII bus.
The PHY Status Interrupt Enable bit provides a
mechanism to generate an interrupt whenever a change of
status is detected in the PHY.
Setting the Timer Interrupt Enable bit will cause an
interrupt to be generated whenever the general timer (GT)
counter reaches zero.
Writing a “1” to this bit causes a software generated
interrupt to be generated. The SWint bit in the Interrupt
Status register is set to indicate the cause of the interrupt.
This bit will always read zero.
Transmit Status Queue Interrupt Enable. Setting this bit
causes an interrupt to be generated whenever a transmit
status is posted to the transmit status queue.
generated whenever a receive-end-of-frame
status, or a receive-end-of-buffer status, or a
receive-header status is written to the receive
status queue.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-59
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