CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet
CP3BT10G38
Specifications of CP3BT10G38
Related parts for CP3BT10G38
CP3BT10G38 Summary of contents
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... Interface Controller Unit USB GPIO Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. TRI-STATE is a registered trademark of National Semiconductor Corporation. ©2005 National Semiconductor Corporation and USB Interfaces in the trade-off between battery size and operating time for handheld and portable applications ...
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General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 CPU Features . . . . . . . ...
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... Schmitt triggers on general purpose inputs Multi-Input Wakeup CP3BT10 Connectivity Processor Selection Guide Speed NSID Temp. Range (MHz) CP3BT10G38 24 -40° to +85°C CP3BT10G38X 24 -40° to +85°C CP3BT10K38X 24 -40° to +85°C CP3BT10K38Y 24 -40° to +85°C T&R = Tape and Reel ...
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Device Overview The CP3BT10 connectivity processor is complete micro- computer with all system timing, interrupt logic, program memory, data memory, I/O ports included on-chip, making them well-suited to a wide range of embedded applications. The block diagram on page ...
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MULTI-INPUT WAKE-UP The Multi-Input Wake-Up (MIWU) module can be used for either of two purposes: to provide inputs for waking up (ex- iting) from the Halt, Idle, or Power Save mode provide general-purpose edge-triggered maskable interrupts from ...
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... CP3BT10 applications, including the IAR Embedded Workbench, iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth Development Board, Bluetooth Protocol Stack, and Applica- tion Software. See your National Semiconductor sales rep- resentative for current information on availability and features of emulation equipment and evaluation boards. 6 ...
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Device Pinouts X1CKI/BBCLK 12 MHz Crystal or Ext. Clock X1CKO X2CKI 32.768 kHz Crystal X2CKO AVCC AGND CP3BT10 Power VCC 2 Supply (LQFP-100) IOVCC 4 GND 6 PIO/RFSYNC Chip Reset RESET TMS TDI JTAG I/F to PI6/BTSEQ2/WUI9 TDO Debugger/ ...
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Pin Name A4 VCC X2CKI X2CKO GND AVCC AGND IOVCC X1CKO X1CKI GND RFDATA PI0 PI1 PI2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND IOVCC PI3 PI4 PI5 PI6 PI7 PG0 PG1 PC0 PG2 ...
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Table 2 Pin Assignments for 100-Pin Package Pin Name Alternate Function(s) PC5 PC6 PC7 PG5 TMS TCK TDI GND IOVCC ENV2 SEL0 SCL SDA TDO D- D+ UVCC UGND RDY SEL1 SEL2 SELIO A21 A20 PH0 PH1 PH2 PH3 ENV0 ...
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Pin Name PH4 PH5 Note 1: The ENV0, ENV1, ENV2, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The RESET input has a weak pulldown. Note 3: These functions are ...
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Pin Name UGND RDY PH0 PH1 PH2 PH3 ENV0 VCC GND RESET PH4 PH5 Note 1: The ENV0, ENV1 and ENV2, TCK, TDI and TMS pins each have a weak pull-up to keep the input from floating. Note 2: The ...
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PIN DESCRIPTIONS Some pins may be enabled as general-purpose I/O-port pins or as alternate functions associated with specific pe- ripherals or interfaces. These pins may be individually con- Table 4 CP3BT10 Pin Descriptions for the 100-Pin LQFP Package Name ...
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Name Pins I/O Primary Function PH3 1 I/O Generic I/O PH4 1 I/O Generic I/O PH5 1 I/O Generic I/O PH6 1 I/O Generic I/O PH7 1 I/O Generic I/O RFDATA 1 I/O Bluetooth RX/TX Data Pin PI0 1 I/O ...
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Name Pins I Output External Memory Read Special mode select input with in- ENV0 1 I/O ternal pull-up during reset Special mode select input with in- ENV1 1 I/O ternal pull-up during reset Special mode select input with ...
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Name Pins I/O Primary Function PH0 1 I/O Generic I/O PH1 1 I/O Generic I/O PH2 1 I/O Generic I/O PH3 1 I/O Generic I/O PH4 1 I/O Generic I/O PH5 1 I/O Generic I/O PH6 1 I/O Generic I/O ...
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CPU Architecture The CP3BT10 uses the CR16C third-generation 16-bit CompactRISC processor core. The CPU implements a Re- duced Instruction Set Computer (RISC) architecture that al- lows an effective execution rate one instruction per clock cycle. For ...
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Interrupt Base Register (INTBASE) The INTBASE register holds the address of the dispatch ta- ble for exceptions. The dispatch table can be located any- where in the CPU address space. When loading the INTBASE register, bits ...
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CONFIGURATION REGISTER (CFG) The CFG register is used to enable or disable various oper- ating modes and to control optional on-chip caches. Be- cause the CP3BT10 does not have cache memory, the cache control bits in the CFG register ...
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ADDRESSING MODES The CR16C CPU core implements a load/store architec- ture, in which arithmetic and logical instructions operate on register operands. Memory operands are made accessible in registers using load and store instructions. For efficient implementation of I/O-intensive embedded ...
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STACKS A stack is a last-in, first-out data structure for dynamic stor- age of data and addresses. A stack consists of a block of memory used to hold the data and a pointer to the top of the stack. ...
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Mnemonic Operands MOVi Rsrc/imm, Rdest MOVXB Rsrc, Rdest MOVZB Rsrc, Rdest MOVXW Rsrc, RPdest MOVZW Rsrc, RPdest MOVD imm, RPdest RPsrc, RPdest ADD[U]i Rsrc/imm, Rdest ADDCi Rsrc/imm, Rdest ADDD RPsrc/imm, RPdest MACQWa Rsrc1, Rsrc2, RPdest MACSWa Rsrc1, Rsrc2, RPdest MACUWa ...
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Mnemonic ASHUD Rsrc/imm, RPdest LSHi Rsrc/imm, Rdest LSHD Rsrc/imm, RPdest SBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs CBITi Iposition, disp(Rbase) Iposition, disp(RPbase) Iposition, (Rindex)disp(RPbasex) Iposition, abs Iposition, (Rindex)abs TBIT Rposition/imm, Rsrc TBITi Iposition, disp(Rbase) Iposition, disp(RPbase) ...
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Mnemonic Operands RETX PUSH imm, Rsrc, RA POP imm, Rdest, RA POPRET imm, Rdest, RA LOADi disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest LOADD disp(Rbase), Rdest abs, Rdest (Rindex)abs, Rdest (Rindex)disp(RPbasex), Rdest disp(RPbase), Rdest STORi Rsrc, disp(Rbase) ...
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Mnemonic STORMP imm3 DI EI EIWAIT NOP WAIT www.national.com Table 7 Instruction Set Summary Operands Store registers (R2-R5, R8-R11) to memory starting at (R7,R6) Disable maskable interrupts Enable maskable interrupts Enable maskable interrupts and wait for interrupt ...
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Memory The CP3BT10 supports a uniform 16M-byte linear address space. Table 8 lists the types of memory and peripherals that occupy this memory space. Unlisted address ranges Start End Address Address 00 0000h 03 FFFFh 04 0000h 0D FFFFh ...
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BUS INTERFACE UNIT (BIU) The BIU controls the interface between the CPU core bus and those on-chip modules which are mapped into BIU zones. These on-chip modules are the flash program mem- ory and the I/O zone. The BIU ...
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I/O Zone Configuration Register (IOCFG) The IOCFG register is a word-wide, read/write register that controls the timing and bus characteristics of accesses to the 256-byte I/O Zone memory space (FF FB00h to FF FBFFh). The registers associated with Port ...
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IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle, when the new bus cycle accesses a dif- ferent zone. No idle cycles are required for on- chip accesses. – ...
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Static Zone 2 Configuration Register (SZCFG2) The SZCFG2 register is a word-wide, read/write register that controls the timing and bus characteristics for off-chip accesses selected with the SEL2 output signal. At reset, the register is initialized to 069Fh. The ...
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System Configuration Registers The system configuration registers control and provide sta- tus for certain aspects of device setup and operation, such as indicating the states sampled from the ENV[2:0] inputs. The system configuration registers are listed in Table 11. ...
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Flash Memory The flash memory consists of the flash program memory and the flash data memory. The flash program memory is further divided into the Boot Area and the Code Area. A special protection scheme is applied to the ...
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Each block consists of sixteen 8K-byte sections. Write ac- cess by the CPU to Main Block 0 and Main Block 1 is con- trolled by the corresponding bits in the FM0WER and FM1WER registers, respectively. The least significant bit in ...
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Write to an address within the desired page. 5. Wait until the FMBUSY bit becomes clear again. 6. Check the Erase Error (EERR) bit to confirm successful erase of the page. The EERR bit is in the FMSTAT or ...
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USB_ENABLE The USB_ENABLE bit can be used to force an external USB transceiver into its low-power mode. The power mode is dependent on the USB controller status, the USB_ENABLE bit in the MCFG register (see Section 7.1), and the USB_ENABLE ...
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If a majority of the WR- PROT bits are set, write access is allowed. 8.5 FLASH MEMORY INTERFACE REGISTERS There is a separate interface for the program flash and data flash memories. The same set of registers ...
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Flash Memory Information Block Data Register (FMIBDR/FSMIBDR) The FMIBDR register holds the 16-bit data for read or write access to an information block. The FMIBDR register is cleared after device reset. The CPU bus master has read/ write access ...
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Flash Memory Control Register (FMCTRL/ FSMCTRL) This register controls the basic functions of the Flash pro- gram memory. The register is clear after device reset. The CPU bus master has read/write access to this register ...
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PERR The Program Error bit indicates whether an error has occurred during programming. After a programming error occurs, software can clear the PERR bit by writing it. Writing the PERR bit has no effect. ...
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Flash Memory Transition Time Reload Register (FMTRAN/FSMTRAN) The FMTRAN/FMSTRAN register is a byte-wide read/write register that controls some program/erase transition times. Software must not modify this register while program/erase operation is in progress (FMBUSY set). At reset, this regis- ...
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Flash Memory Recovery Time Reload Register (FMRCV/FSMRCV) The FMRCV/FSMRCV register is a byte-wide read/write register that controls the recovery delay time between two flash memory accesses. Software must not modify this reg- ister while a program/erase operation is in ...
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DMA Controller The DMA Controller (DMAC) has a register-based program- ming interface, as opposed to an interface based on I/O control blocks. After loading the registers with source and destination addresses, as well as block size and type of ...
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The maximum bus throughput in intermittent mode is one transfer for every three System Clock cycles. The max- imum bus throughput in continuous mode is one transfer for every clock cycle. The I/O device which made the DMA request ...
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If the DMASTAT.VLD bit is clear: 1. The transfer operation terminates. 2. The channel sets the DMASTAT.OVR bit. 3. The DMASTAT.CHAC bit is cleared interrupt is generated DMACNTLn.EOVR bit. The DMACNTLn.CHEN bit must be cleared before loading the ...
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Table 20 DMA Controller Registers Name Address ADCA2 FF F840h ADRA2 FF F844h ADCB2 FF F848h ADRB2 FF F84Ch BLTC2 FF F850h BLTR2 FF F854h DMACNTL2 FF F85Ch DMASTAT2 FF F85Eh ADCA3 FF F860h ADRA3 FF F864h ADCB3 FF F868h ...
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Block Length Register (BLTRn) The Block Length register is a 16-bit, read/write register. It holds the number of DMA transfers to be performed for the next block. Writing this register automatically sets the DM- ASTAT.VLD bit. 15 Block Length ...
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DMA Status Register (DMASTAT) The DMA status register is a byte-wide, read register that holds the status information for the DMA channel n. This register is cleared at reset. The reserved bits always return zero when read. The VLD, ...
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Interrupts The Interrupt Control Unit (ICU) receives interrupt requests from internal and external sources and generates interrupts to the CPU. Interrupts from the timers, UARTs, Microwire/ SPI interface, and Multi-Input Wake-Up are all maskable in- terrupts. The highest-priority interrupt ...
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External NMI Trap Control and Status Register (EXNMI) The EXNMI register is a byte-wide read/write register. It in- dicates the current value of the NMI pin and controls the NMI interrupt trap generation based on a falling edge of ...
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Interrupt Status Register 0 (ISTAT0) The ISTAT0 register is a word-wide read-only register. It in- dicates which maskable interrupt inputs to the ICU are ac- tive. These bits are not affected by the state of the corresponding IENA bits. ...
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All reserved or unused interrupt vectors should point to a default or error interrupt handlers. 10.5 NESTED INTERRUPTS Nested NMI interrupts are always enabled. Nested maskable interrupts are disabled by default, however an in- terrupt handler can allow nested maskable ...
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Triple Clock and Reset The Triple Clock and Reset module generates a 12 MHz Main Clock and a 32.768 kHz Slow Clock from external crystal networks or external clock sources. It provides vari- ous clock signals for the rest ...
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EXTERNAL CRYSTAL NETWORK An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock, unless an external clock signal is driven on the X1CKI pin. A similar external crystal network may be used ...
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The Stop Main Osc signal from the Power Management Module stops and starts the high-frequency oscillator. When this signal is asserted, it presets the 14-bit timer to 3FFFh and stops the high-frequency oscillator. When the signal goes inactive, the high-frequency ...
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The external reset circuits presented in the following sec- tions provide varying levels of additional fault tolerance and expandability and are presented as possible examples of solutions to be used with the CP3BT10 important to note, however, that ...
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Fault-Tolerant External Reset An external reset circuit based on the LM3710 Microproces- sor Supervisory Circuit is shown in Figure 8. It provides a high level of fault tolerance in that it provides the ability to monitor both the VCC ...
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ACE1 When the Auxiliary Clock Enable bit is set and a stable Main Clock is provided, the Auxiliary Clock 1 prescaler is enabled and generates the first Auxiliary Clock. When the ACE1 bit is clear or the Main Clock is ...
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Power Management The Power Management Module (PMM) improves the effi- ciency of the CP3BT10 by changing the operating mode (and therefore the power consumption) according to the re- quired level of device activity. The device implements four power modes: ...
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Altogether, three mechanisms control whether the high-fre- quency oscillator is active, and four mechanisms control whether the PLL is active: HCC Bits: The HCCM and HCCH bits in the PMMCR register may be used to disable the high-frequency oscil- lator ...
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This bit must be set in Idle and Halt modes. – 0 PLL is not disabled in Power Save mode, unless disabled by the HCC mechanism or the PLLPWD bit. – 1 PLL is disabled in ...
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NMI) that causes pro- gram execution to resume. 12.7.1 Active Mode to Power Save Mode A transition from Active mode to Power Save mode is per- formed by writing the PMMCR.PSM ...
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Multi-Input Wake-Up The Multi-Input Wake-Up Unit (MIWU) monitors its 16 input channels for a software-selectable trigger condition. On de- tection of a trigger condition, the module generates an inter- rupt request and if enabled, a wake-up request. A wake-up ...
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WUI0 WUI15 WKEDG Figure 10. Multi-Input Wake-Up Module Block Diagram 13.1.2 Wake-Up Enable Register (WKENA) The Wake-Up Enable (WKENA) register is a word-wide read/write register that individually enables or disables wake-up events from the MIWU channels. The WKENA reg- ister ...
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Wake-Up Interrupt Control Register 2 (WKICTL2) The WKICTL2 register is a word-wide read/write register that selects the interrupt request signal for the associated MIWU channels WUI15 to WUI8. At reset, the WKICTL2 register is cleared, which selects MIWU Interrupt ...
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Input/Output Ports Each device has software-configurable I/O pins, or- ganized into five 8-bit ports. The ports are named Port B, Port C, Port G, Port H, and Port I. In addition to their general-purpose I/O capability, ...
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Table 30 Port Registers Name Address Port B Alternate PBALT FF FB00h Function Register Port B Direction PBDIR FF FB02h Port B Data Input PBDIN FF FB04h Port B Data Output PBDOUT FF FB06h Port B Weak Pull-Up PBWPU FF ...
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Port Alternate Function Register (PxALT) The PxALT registers control whether the port pins are used for general-purpose I/O or for their alternate function. Each port pin can be controlled independently. A clear bit in the alternate function register causes ...
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Port High Drive Strength Register (PxHDRV) The PxHDRV register is a byte-wide, read/write register that controls the slew rate of the corresponding pins. The high drive strength function is enabled when the corresponding bits of the PxHDRV register are ...
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... LMX5252 and other RF transceiver chips For a detailed description of the interface to the LMX5252, consult the LMX5252 data sheet which is available from the National Semiconductor wireless group. National provides software libraries for using the Bluetooth LLC. Documenta- tion for the software libraries is also available from National Semiconductor ...
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The RFSYNC signal is the alternate function of the general- purpose I/O pin PI0. At reset, this pin is in TRI-STATE mode. Software must enable the alternate ...
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Write Operation When the R/W bit is clear, the 16 bits of the data field are shifted out of the CP3BT10 on the falling edge of SCLK. Data is sampled by the radio chip on the rising edge of SCLK. ...
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SDAT SCLK SLE SDAT SCLK SLE An example of a 32-bit write is shown in Table 32. In this ex- ample, the 32-bit value FFFF DC04h ...
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LMX5251 POWER-UP SEQUENCE To power-up a Bluetooth system based on the CP3BT10 and LMX5251 devices, the following sequence must be per- formed: 1. Apply VDD to the LMX5251. 2. Apply IOVCC and VCC to the CP3BT10. 3. Drive the ...
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RESET RFDATA t5 t3 RFCE t1 BBCLK t2 BPOR B3k2 SLE t4 SCLK SDAT Figure 23. LMX5252 Power-Up Sequence 15.5 BLUETOOTH SLEEP MODE The Bluetooth controller is capable of putting itself into a sleep mode for a specified number of ...
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BLUETOOTH SHARED DATA RAM The shared data RAM is a 4.5K memory-mapped section of RAM that contains the link control data, RF programming look-up table, and the link payload. This RAM can be read and written in the same ...
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USB Controller The USB node is an integrated USB node controller that fea- tures enhanced DMA support with many automatic data handling features compatible with USB specification versions 1.0 and 1.1. It integrates the required USB transceiver, ...
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ENDPOINT OPERATION 16.2.1 Address Detection Packets are broadcast from the host controller to all nodes on the USB network. Address detection is implemented in hardware to allow selective reception of packets and to per- mit optimal use of CPU ...
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Bidirectional Control Endpoint FIFO0 Operation FIFO0 should be used for the bidirectional control endpoint 0. It can be configured to receive data sent to the default ad- dress with the DEF bit in the EPC0 register. Isochronous transfers are not ...
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Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2, RXFIFO3) The Receive FIFOs for endpoints 2, 4, and 6 support bulk, interrupt, and isochronous USB packet transfers larger than the actual FIFO size. If the packet length exceeds the FIFO size, software must ...
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Table 37 USB Controller Registers Name Address Description Endpoint Control 0 EPC0 FF FDC0h Endpoint Control 1 EPC1 FF FDD0h Endpoint Control 2 EPC2 FF FDD8h Endpoint Control 3 EPC3 FF FDE0h Endpoint Control 4 EPC4 FF FDDE8h Endpoint Control ...
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NAT The Node Attached indicates that this node is ready to be detected as attached to USB. When clear, the transceiver forces SE0 on the USB node controller to prevent the hub (to which this node is connected) from detecting ...
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Main Event Register (MAEV) The Main Event Register summarizes and reports the main events of the USB transactions. This register provides read- only access. The MAEV register is clear after reset INTR RX_EV ULD ...
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SD3 The Suspend Detect 3 ms bit is set after IDLE have been detected on the upstream port, indicating that the device should be sus- pended. The suspend occurs under software control by writing the suspend value ...
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Receive Event Register (RXEV) The RXEV register reports the current status of the FIFO, used by the three Receive Endpoints. The RXEV register is clear after reset. It provides read-only access from the CPU bus RXOVRRN ...
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FIFO Warning Event Register (FWEV) The FWEV register signals whether a receive or transmit FIFO has reached its warning limit. It reports the status for all FIFOs, except for the Endpoint 0 FIFO warning limit can be ...
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MF The Missed SOF bit is set when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. The MF bit provides read-only access. ...
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DTGL The DMA Toggle bit is used to determine the initial state of Automatic DMA (ADMA) opera- tions. Software initially sets this bit if starting with a DATA1 operation, and clears this bit if starting with a DATA0 operation. Writes ...
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DMA Mask Register (DMAMSK) Any set bit in the DMAMSK register enables automatic set- ting of the DMA bit in the ALTEV register when the respec- tive event in the DMAEV register occurs. Otherwise, setting the DMA bit is ...
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The erroneous packet is ignored and not transferred via DMA. If this bit is cleared, automatic error handling ceases. 16.3.24 Endpoint Control 0 Register (EPC0) The EPC0 register controls the mandatory Endpoint clear ...
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FLUSH Writing the Flush FIFO bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using ...
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FLUSH Writing 1 to the Flush bit flushes all data from the control endpoint FIFOs, resets the end- point to Idle state, clears the FIFO read and write pointer, and then clears itself. If the end- point is currently using ...
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ACK_STAT The Acknowledge Status bit is valid when the TX_DONE bit is set. The meaning of the ACK_STAT bit differs depending on whether ISO or non-ISO operation is used (as selected by the ISO bit in the EPCn register). Non-Isochronous ...
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TFWL The Transmit FIFO Warning Limit bits specify how many more bytes can be transmitted from the respective FIFO before an underrun con- dition occurs. If the number of bytes remaining in the FIFO is equal to or less than ...
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Receive Command Register n (RXCn) Each of the receive endpoints (2, 4, and 6) has one RXCn register. The registers provide read/write access from the CPU bus. Reading reserved bits returns undefined data. Af- ter reset clear. ...
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Advanced Audio Interface The Advanced Audio Interface (AAI) provides a serial syn- chronous, full duplex interface to codecs and similar serial devices. The transmit and receive paths may operate asyn- chronously with respect to each other. Each path uses ...
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Asynchronous Mode In asynchronous mode, the receive and transmit paths of the audio interface operate independently, with each path using its own bit clock and frame sync signal. Independent clocks for receive and transmit are only used when the ...
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The transmitter only drives data on the STD pin during slots which have been assigned to this interface. During all other slots, the STD output is in high-impedance mode, and data can be driven by other devices. The assignment of ...
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SFS SRCLK (auxiliary frame sync) SRFS (auxiliary frame sync) Data from/to Data from/to Data from/to STD/SRD Codec 1 Codec 2 Codec 3 Slot 0 Slot 1 Slot 2 Frame Figure 34. Accessing Three Devices in Network Mode 17.3 BIT CLOCK ...
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Figure 35 shows the interrupt structure of the AAI. RXIE RXIP = 1 RXEIE RXEIP = 1 TXIE TXIP = 1 TXEIE TXEIP = 1 Figure 35. AAI Interrupt Structure 17.5.3 Normal Mode In normal mode, each frame sync signal ...
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Network Mode In network mode, each frame sync signal marks the begin- ning of new frame. Each frame can consist four slots. The audio interface ...
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If the corresponding Frame Sync Select (FSS) bit in the Au- dio ...
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IOM-2 Mode The AAI can operate in a special IOM-2 compatible mode to allow to connect to an external ISDN controller device. In this IOM-2 mode, the AAI can only operate as a slave, i.e. the bit clock and ...
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Freeze Mode The audio interface provides a FREEZE input, which allows to freeze the status of the audio interface while a develop- ment system examines the contents of the FIFOs and reg- isters. When the FREEZE input is asserted, ...
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Audio Receive FIFO Register (ARFR) The Audio Receive FIFO register shows the receive FIFO location currently addressed by the Receive FIFO Read Pointer (RRP). The receive FIFO receives 8-bit or 16-bit data from the Audio Receive Shift Register (ARSR), ...
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Audio Global Configuration Register (AGCR) The AGCR register controls the basic operation of the inter- face. The CPU bus master has read/write access to the AGCR register. After reset, this register is clear IEBC ...
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IOM2 The IOM-2 Mode bit selects the normal PCM interface mode or a special IOM-2 mode used to connect to external ISDN controller devic- es. The AAI can only operate as a slave in the IOM-2 mode, i.e. the bit ...
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Audio Receive Status and Control Register (ARSCR) The ARSCR register is used to control the operation of the receiver path of the audio interface. It also holds bits which report the current status of the receive FIFO. The CPU ...
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Audio Transmit Status and Control Register (ATSCR) The ASCR register controls the basic operation of the inter- face. It also holds bits which report the current status of the audio communication. The CPU bus master has read/write access to ...
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Audio Clock Control Register (ACCR) The ACCR register is used to control the bit timing of the au- dio interface. After reset, this register is clear. 7 FCPRS 15 BCPRS CSS The Clock Source Select bit selects one out ...
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CVSD/PCM Conversion Module The CVSD/PCM module performs conversion between CVSD data and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification and the PCM en- coding may be 8-bit µ-Law, 8-bit A-Law, or 13-bit ...
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If the module is only used for PCM conversions, the CVSD clock can be disabled by clearing the CVSD Clock Enable bit (CLKEN) in the control register. 18.3 CVSD CONVERSION The CVSD/PCM converter module transforms either 8-bit logarithmic or 13- ...
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The CVSD/PCM module only supports indirect DMA trans- fers. Therefore, transferring PCM data between the CVSD/ PCM module and another on-chip module requires two bus cycles. The trigger for DMA may also trigger an interrupt if the cor- responding enable ...
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Logarithmic PCM Data Input Register (LOGIN) The LOGIN register is an 8-bit wide write-only register used to receive 8-bit logarithmic PCM data from the periph- eral bus and convert it into 13-bit linear PCM data. 7 LOGIN ...
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DMAPI The DMA Enable for PCM In bit enables hard- ware DMA control for writing PCM data into the PCMIN register. If cleared, DMA support is disabled. After reset, this bit is clear. 0 – PCM input DMA disabled. 1 ...
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UART Module The UART module is a full-duplex Universal Asynchronous Receiver/Transmitter that supports a wide range of soft- ware-programmable baud rates and data formats. It han- dles automatic parity generation and several error detection schemes. The UART module offers ...
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RSFT register are copied into the URBUF register and the Receive Buffer Full bit (URBF) is set. The URBF bit is automatically reset when software reads the character Control and Error Detection Generator/Checker Sample ...
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UART Frame Select register. The value of the ninth bit received is read from URB9 in the UART Status Register. 19.2.3 Diagnostic Mode The Diagnostic mode is available for testing of the UART. In this mode, the TXD and ...
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Table 44 Prescaler Factors (Continued) Prescaler Select Prescaler Factor 11010 11011 11100 11101 11110 11111 A prescaler factor of zero corresponds to “no clock.” The “no clock” condition is the UART power down mode, in which the UART clock is ...
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UERI bit. However, receive error interrupts should be en- abled (the UEEI bit is set) to allow detection of receive errors when DMA is used. 19.2.8 Break Generation and Detection ...
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UART Frame Select Register (UFRS) The UFRS register is a byte-wide, read/write register that controls the frame format, including the number of data bits, number of stop bits, and parity type. This register is cleared upon reset. The register ...
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UART Status Register (USTAT) The USTAT register is a byte-wide, read-only register that contains the receive and transmit status bits. This register is cleared upon reset. Any attempt by software to write to this register is ignored. The register ...
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UEEI The Enable Receive Error Interrupt bit, when set, enables generation of an interrupt when the hardware sets the UERR bit in the USTAT register. 0 – Receive error interrupt disabled. 1 – Receive error interrupt enabled. 19.3.9 UART Oversample ...
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BAUD RATE CALCULATIONS The UART baud rate is determined by the System Clock fre- quency and the values in the UOVR, UPSR, and UBAUD registers. Unless the System Clock is an exact multiple of the baud rate, there will ...
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SYS_CLK = 8 MHz Baud Rate %err 300 7 401 9.5 0.00 600 12 1111 1.0 0.01 1200 12 101 5.5 0.01 1800 8 101 5.5 0.01 2000 16 250 1.0 0.00 2400 11 303 1.0 0.01 ...
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Microwire/SPI Interface Microwire/Plus is a synchronous serial communications protocol, originally implemented in National Semiconduc- ® tor's COP8 and HPC families of microcontrollers to mini- mize the number of connections, and therefore the cost, of communicating with peripherals. GPIO I/O ...
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Interrupt Request Write Data Write Data System Clock 20.1.1 Shifting The Microwire interface is a full duplex transmitter/receiver. A 16-bit shifter, which can be split into a low and high byte, is used for both transmitting and receiving. In 8-bit ...
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SCIDL bit equal to 0 and equal to 1. Note that when data is shifted out on MDODI (master mode) or MDIDO (slave mode) on the leading edge of the MSK clock, ...
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MSK Shift Out MSB Data Out Sample Point MSB Data In 20.3 SLAVE MODE In Slave mode, the MSK pin is an input for the shift clock MSK. MDIDO is placed in TRI-STATE mode when MWCS is inactive. Data transfer ...
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Microwire Control Register (MWCTL1) The MWCTL1 register is a word-wide, read/write register used to control the Microwire module. To avoid clock glitch- es, the MWEN bit must be clear while changing the states of any other bits in the ...
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EIR The Enable Interrupt for Read bit controls whether an interrupt is generated when the read buffer becomes full. When set, an inter- rupt is generated when the Read Buffer Full bit (MWSTAT.RBF) is set. Otherwise, no inter- rupt is ...
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ACCESS.bus Interface The ACCESS.bus interface module (ACB two-wire se- rial interface compatible with the ACCESS.bus physical lay- er. It permits easy interfacing to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D ...
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Acknowledge Cycle The Acknowledge Cycle consists of two signals: the ac- knowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiv- ing device (Figure 57). Acknowledgment Signal from Receiver SDA MSB 3 ...
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ACB FUNCTIONAL DESCRIPTION The ACB module provides the physical layer for an AC- CESS.bus compliant serial interface. The module is config- urable as either a master or slave device slave, the ACB module may issue a request ...
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The bits that can cause a stall in master mode are: Negative acknowledge after sending a byte (ACBSTNEGACK = 1). ACBST.SDAST bit is set. If the ACBCTL1.STASTRE bit is set, after a successful start (ACBST.STASTR = 1). Repeated Start A ...
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Power Down When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status. If the ACB is enabled (ACBCTL2.ENABLE = 1) on detection of a Start Condition, a wake-up signal ...
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MASTER The Master bit indicates that the module is currently in master mode set when a re- quest for bus mastership succeeds cleared upon arbitration loss (BER is set) or the recognition of a Stop Condition. ...
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BB The Bus Busy bit indicates the bus is busy set when the bus is active (i.e., a low level on either SDA or SCL Start Condition cleared when the module is disabled, ...
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INTEN The Interrupt Enable bit controls generating ACB interrupts. When the INTEN bit is cleared ACB interrupt is disabled. When the INTEN bit is set, interrupts are enabled. 0 – ACB interrupts disabled. 1 – ACB interrupts enabled. An interrupt ...
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ACB Own Address Register 1 (ACBADDR1) The ACBADDR1 register is a byte-wide, read/write register that holds the module’s first ACCESS.bus address. After re- set, its value is undefined SAEN ADDR ADDR The Own Address field holds the ...
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Timing and Watchdog Module The Timing and Watchdog Module (TWM) generates the clocks and interrupts used for timing periodic functions in the system; it also provides Watchdog protection over soft- ware execution. The TWM is designed to provide flexibility ...
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WATCHDOG OPERATION The Watchdog is an 8-bit down counter that operates on the rising edge of a specified clock source. At reset, the Watch- dog is disabled; it does not count and no Watchdog signal is generated. A write ...
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Timer and Watchdog Configuration Register (TWCFG) The TWCFG register is a byte-wide, read/write register that selects the Watchdog clock input and service method, and also allows the Watchdog registers to be selectively locked. A locked register cannot be read ...
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TWMT0 Control and Status Register (T0CSR) The T0CSR register is a byte-wide, read/write register that controls Timer T0 and shows its current status. At reset, the non-reserved bits of the register are cleared. The register format is shown below. ...
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Multi-Function Timer The Multi-Function Timer module contains a pair of 16-bit timer/counters. Each timer/counter unit offers a choice of clock sources for operation and can be configured to oper- ate in any of the following modes: Processor-Independent Pulse Width ...
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Counter Clock Source Select There are two clock source selectors that allow software to independently select the clock source for each of the two 16-bit counters from any one of the following sources: No clock (which stops the counter) Prescaled ...
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Mode 1: Processor-Independent PWM Mode 1 is the Processor-Independent Pulse Width Modula- tion (PWM) mode, which generates pulses of a specified width and duty cycle, and which also provides a separate general-purpose timer/counter. Figure block diagram ...
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Mode 2: Input Capture Mode 2 is the Input Capture mode, which measures the elapsed time between occurrences of external events, and which also provides a separate general-purpose timer/ counter. Figure block diagram of the Multi-Function ...
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Mode 3: Dual Independent Timer/Counter Mode 3 is the Dual Independent Timer mode, which gener- ates system timing signals or counts occurrences of exter- nal events. Timer 1 Clock Timer 2 Clock Figure 65. Dual-Independent Timer/Counter Mode Timer/Counter 1 ...
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TIMER INTERRUPTS Each Multi-Function Timer unit has four interrupt sources, designated and D. Interrupt sources A, B, and C are mapped into a single system interrupt called Timer Interrupt 1, while interrupt source D is mapped ...
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TIMER REGISTERS Table 53 lists the CPU-accessible registers used to control the Multi-Function Timers. Table 53 Multi-Function Timer Registers Name Address TPRSC FF FF48h TCKC FF FF4Ah TCNT1 FF FF40h TCNT2 FF FF46h TCRA FF FF42h TCRB FF FF44h ...
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Reload/Capture A Register (TCRA) The TCRA register is a word-wide, read/write register that holds the reload or capture value for Timer/Counter 1. The register contents are not affected by a reset and are un- known after power-up. 15 TCRA ...
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TBPND The Timer Interrupt Source B Pending bit indi- cates that timer interrupt condition B has oc- curred. For an explanation of interrupt conditions and D, see Table 51. This bit can be set by hardware or ...
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Versatile Timer Unit (VTU) The VTU contains four fully independent 16-bit timer sub- systems. Each timer subsystem can operate either as dual 8-bit PWM timers single 16-bit PWM timer 16- bit counter with 2 ...
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Dual 8-bit PWM Mode Each timer subsystem may be configured to generate two fully independent PWM waveforms on the respective TIOx pins. In this mode, the counter COUNTx is split and oper- ates as two independent 8-bit counters. Each ...
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The two I/O pins associated with a timer subsystem function as independent PWM outputs in the dual 8-bit PWM mode PWM timer is stopped using its associated MODE.TxRUN bit the following actions result: The associated TIOx pin will ...
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Figure 70 illustrates the configuration of a timer subsystem while operating in capture mode. The numbering in Figure 70 refers to timer subsystem 1 but equally applies to the other three timer subsystems. 7 C1PRSC = = Prescaler Counter T1RUN ...
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VTU REGISTERS The VTU contains a total of 19 user accessible registers, as listed in Table 55. All registers are word-wide and are initial- ized to a known value upon reset. All software accesses to the VTU registers must ...
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I/O Control Register 1 (IO1CTL) The I/O Control Register 1 (IO1CTL word-wide read/ write register. The register controls the function of the I/O pins TIO1 through TIO4 depending on the selected mode of operation. The register is ...
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IxCEN The Timer x Interrupt C Enable bit controls in- terrupt requests triggered on the correspond- ing IxCPD bit being set. The associated IxCPD bit will be updated regardless of the value of the IxCEN bit. 0 – Disable system ...
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Counter Register n (COUNTx) The Counter (COUNTx) registers are word-wide read/write registers. There are a total of four registers called COUNT1 through COUNT4, one for each of the four timer sub- systems. Software may read the registers at any ...
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Register Map Table detailed memory map showing the specific memory address of the memory, I/O ports, and registers. The table shows the starting address, the size, and a brief description of each memory block and register. ...
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Register Name WTPTC_1SLOT WTPTC_3SLOT WTPTC_5SLOT SEQ_RESET SEQ_CONTINUE RX_STATUS CHIP_ID INT_VECTOR SYSTEM_CLK_EN LINKTIMER_WR_RD LINKTIMER_SELECT LINKTIMER_STATUS_EXP_FLAG LINKTIMER_STATUS_RD_WR_FLAG LINKTIMER_ADJUST_PLUS LINKTIMER_ADJUST_MINUS SLOTTIMER_WR_RD MCNTRL FAR NFSR MAEV MAMSK ALTEV ALTMSK TXEV TXMSK RXEV RXMSK NAKEV NAKMSK FWEV FWMSK FNH FNL DMACNTRL Access Size Address Type ...
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Register Name DMAEV DMAMSK MIR DMACNT DMAERR EPC0 TXD0 TXS0 TXC0 RXD0 RXS0 RXC0 EPC1 TXD1 TXS1 TXC1 EPC2 RXD1 RXS1 RXC1 EPC3 TXD2 TXS2 TXC2 EPC4 RXD2 RXS2 RXC2 EPC5 TXD3 TXS3 TXC3 EPC6 RXD3 RXS3 RXC3 www.national.com Access ...
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Register Name ADCA0 ADRA0 ADCB0 ADRB0 BLTC0 BLTR0 DMACNTL0 DMASTAT0 ADCA1 ADRA1 ADCB1 ADRB1 BLTC1 BLTR1 DMACNTL1 DMASTAT1 ADCA2 ADRA2 ADCB2 ADRB2 BLTC2 BLTR2 DMACNTL2 DMASTAT2 ADCA3 Access Size Address Type DMA Controller Double FF F800h Read/Write Word Double FF ...
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Register Name ADRA3 ADCB3 ADRB3 BLTC3 BLTR3 DMACNTL3 DMASTAT3 BCFG IOCFG SZCFG0 SZCFG1 SZCFG2 MCFG DBGCFG MSTAT FMIBAR FMIBDR FM0WER FM1WER FMCTRL FMSTAT FMPSR FMSTART FMTRAN FMPROG FMPERASE FMMERASE0 www.national.com Access Size Address Type Double FF F864h Read/Write Word Double ...
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Register Name FMEND FMMEND FMRCV FMAR0 FMAR1 FMAR2 FSMIBAR FSMIBDR FSM0WER FSMCTRL FSMSTAT FSMPSR FSMSTART FSMTRAN FSMPROG FSMPERASE FSMMERASE0 FSMEND FSMMEND FSMRCV FSMAR0 FSMAR1 FSMAR2 CVSDIN CVSDOUT PCMIN PCMOUT LOGIN LOGOUT LINEARIN LINEAROUT Access Size Address Type Byte FF F95Eh ...
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Register Name CVCTRL CVSTAT CVTEST CVRADD CVRDAT CVDECOUT CVENCIN CVENCPR CRCTRL PRSFC PRSSC PRSAC PMMCR PMMSR WKEDG WKENA WKICTL1 WKICTL2 WKPND WKPCL WKIENA PBALT PBDIR PBDIN PBDOUT PBWPU www.national.com Access Size Address Type Word FF FC30h Read/Write Word FF FC32h ...
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Register Name PBHDRV PBALTS PCALT PCDIR PCDIN PCDOUT PCWPU PCHDRV PCALTS PGALT PGDIR PGDIN PGDOUT PGWPU PGHDRV PGALTS PHALT PHDIR PHDIN PHDOUT PHWPU PHHDRV PHALTS PIALT PIDIR PIDIN PIDOUT PIWPU PIHDRV PIALTS Access Size Address Type Byte FF FB0Ah Read/Write ...
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Register Name ARFR ARDR0 ARDR1 ARDR2 ARDR3 ATFR ATDR0 ATDR1 ATDR2 ATDR3 AGCR AISCR ARSCR ATSCR ACCR ADMACR IVCT NMISTAT EXNMI ISTAT0 ISTAT1 IENAM0 IENAM1 UTBUF URBUF UICTRL USTAT UFRS UMDSL1 www.national.com Access Size Address Type Advanced Audio Interface Word ...
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Register Name UBAUD UPSR UOVR UMDSL2 USPOS MWDAT MWCTL1 MWSTAT ACBSDA ACBST ACBCST ACBCTL1 ACBADDR ACBCTL2 ACBADDR2 ACBCTL3 TWCFG TWCP TWMT0 T0CSR WDCNT WDSDM TCNT1 TCRA TCRB Access Size Address Type Byte FF FE4Ch Read/Write Byte FF FE4Eh Read/Write Byte ...
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Register Name TCNT2 TPRSC TCKC TCTRL TICTL TICLR MODE IO1CTL IO2CTL INTCTL INTPND CLK1PS COUNT1 PERCAP1 DTYCAP1 COUNT2 PERCAP2 DTYCAP2 CLK2PS COUNT3 PERCAP3 DTYCAP3 COUNT4 PERCAP4 DTYCAP4 www.national.com Access Size Address Type Word FF FF46h Read/Write Byte FF FF48h Read/Write ...
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Register Bit Fields The following tables show the functions of the bit fields of the device registers. For more information on using these regis- ters, see the detailed description of the applicable function elsewhere in this data sheet. Bluetooth ...
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Bluetooth LLC 7 Registers WTPTC_5SLOT[15:8] SEQ_RESET SEQ_CONTINUE RX_STATUS Reserved HEC Error CHIP_ID INT_VECTOR SYSTEM_CLK_EN LINK_TIMER_WR_RD[7:0] LINK_TIMER_WR_RD[15:8] LINK_TIMER_SELECT LINK_TIMER_STATUS_ EXP_FLAG LINK_TIMER_STATUS_ RD_WR_FLAG LINK_TIMER_AD_JUST _PLUS LINK_TIMER_AD_JUST _MINUS SLOTTIMER_WR_RD Reserved USB 7 6 Registers MCNTRL Reserved FAR AD_EN NFSR MAEV INTR RX_EV MAMSK ...
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USB 7 6 Registers NAKEV OUT[3:0] NAKMSK OUT[3:0] FWEV RXWARN[3:1] FWMSK RXWARN[3:1] FNH MF UL FNL DMACNTRL DEN IGNRXTGL DMAEV Reserved DMAMSK Reserved MIR DMACNT DMAERR AEH EPC0 STALL DEF TXD0 TXS0 Reserved ACK_STAT TX_DONE TXC0 Red RXD0 RXS0 Res. ...
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USB 7 6 Registers RXS2 RX_ERR SETUP RXC2 Reserved EPC5 STALL Reserved TXD3 TXS3 TX_URUN ACK_STAT TX_DONE IGN_ TXC3 ISOMSK EPC6 STALL Reserved RXD3 RXS3 RX_ERR SETUP RXC3 Reserved DMAC 20.. Registers ADCA ADRA ADCB ADRB BLTC N/A ...
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BIU 15 12 Registers BCFG IOCFG Reserved SZCFG0 Reserved SZCFG1 Reserved SZCFG2 Reserved TBI Register 7 TMODE Reserved Flash Program Memory Interface Registers FMIBAR Reserved FMIBDR FM0WER FM1WER FM2WER FM3WER FMCTRL Reserved FMSTAT FMPSR FMSTART Reserved ...
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Flash Program Memory Interface Registers FMAR0 FMAR1 WRPROT FMAR2 Flash Data Memory Interface Registers FSMIBAR FSMIBDR FSM0WER FSM1WER FSM2WER FSM3WER FSMCTRL FSMSTAT FSMPSR FSMSTART FSMTRAN FSMPROG FSMPERASE FSMMERASE0 FSMEND FSMMEND FSMRCV FSMAR0 FSMAR1 WRPROT ...
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CVSD/PCM Registers CVSDIN CVSDOUT PCMIN PCMOUT LOGIN LOGOUT LINEARIN LINEAROUT CVCTRL Reserved CVSTAT Reserved CVTEST CVRADD CVRDAT CVDECOUT CVENCIN CVENCPR CLK3RES 7 Registers CRCTRL Reserved PRSFC Reserved PRSSC PRSAC PMM Register 7 PMMCR HCCH PMMSR 12 11 ...
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MIWU16 Registers WKEDG WKENA WKICTL1 WKINTR7 WKINTR6 WKICTL2 WKINTR15 WKINTR14 WKINTR13 WKINTR12 WKINTR11 WKINTR10 WKPND WKPCL WKIENA GPIO Registers PxALT PxDIR PxDIN PxDOUT PxWPU PxHDRV PxALTS AAI Registers ARSR ATSR ARFR ARDR0 ARDR1 ARDR2 ...
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AAI Registers AISCR Reserved ARSCR RXFWM[3:0] ATSCR TXFWM[3:0] ACCR BCPRS[7:0] ADMACR Reserved ACO[1:0] ICU Registers IVCT Reserved ISTAT0 ISTAT1 IENAM0 IENAM1 UART 7 6 Registers UTBUF ...
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ACB Registers 7 ACBSDA ACBST SLVSTP ACBCST ARPMATCH MATCHAF ACBCTL1 STASTRE ACBADDR SAEN ACBCTL2 ACBADDR2 SAEN ACBCTL3 TWM Registers TWCFG Reserved TWCP Reserved TWMT0 T0CSR Reserved WDCNT Reserved WDSDM Reserved MFT16 ...
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VTU Registers T8 T7 MODE TMOD4 RUN RUN P4 IO1CTL C4EDG POL P7 IO2CTL C7EDG POL INTCTL I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN INTPND I4DPD I4CPD ...
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... Electrical Characteristics 27.1 ABSOLUTE MAXIMUM RATINGS If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distribu- tors for availability and specifications. Supply voltage (VCC) All input and output voltages with re- spect to GND* ESD protection level Allowable sink/source current per signal pin 27 ...
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Symbol Parameter Iccprog Digital Supply Current Active Mode Iccps Digital Supply Current Power Save Mode Iccid Digital Supply Current Idle Mode Iccq Digital Supply Current Halt Mode a. Guaranteed by design b. Test code executing from internal RAM. No peripheral ...
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FLASH MEMORY ON-CHIP PROGRAMMING Symbol Parameter t Program/Erase to NVSTR Setup Time START (NVSTR = Non-Volatile Storage t NVSTR to Program Setup Time TRAN t Programming Pulse Width PROG t Page Erase Pulse Width PERASE t Module Erase Pulse ...
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OUTPUT SIGNAL LEVELS All output signals are powered by the digital supply (VCC). Table 57 summarizes the states of the output signals during the reset state (when VCC power exists in the reset state) and during the Power Save ...
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X1CKI X2CKI CLK NMI CLK RESET www.national.com t X1p t t X1h X1l t X2p t t X2h X2l Figure 72. Clock Timing Figure 73. NMI Signal Timing t RST Figure 74. Non-Power-On Reset ...
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I/O PORT TIMING Symbol Figure Description t 76 Input Setup Time Input Hold Time Output Valid Time COv1 Port Input Port Output Table 59 I/O Port Signals Reference I/O Port Input Signals Before ...
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ADVANCED AUDIO INTERFACE (AAI) TIMING Table 60 Advanced Audio Interface (AAI) Signals Symbol Figure Description t 77,79 Receive Data Setup Time RDS t 77,79 Receive Data Hold Time RDH t 77 Frame Sync Setup Time FSS t 77 Frame ...
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SCK SFS STD t TDV Figure 78. Transmit Timing, Short Frame Sync SRCLK 0 1 SRFS t FSVH SRD 0 t RDH t RDS Figure 79. Receive Timing, Long Frame Sync SCK 0 1 SFS STD 0 t TDV Figure ...
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MICROWIRE/SPI TIMING Symbol Figure Description t 81 Microwire Clock High MSKh t 81 Microwire Clock Low MSKl 81 t Microwire Clock Period MSKp MSK Hold (slave only) MSKh t 81 MSK Setup (slave only) MSKs 81 ...
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Symbol Figure Description t 81 Microwire Data Out Valid MDOv MDODI to MDIDO 85 t MITOp (slave only) MSK t MSKh t MSKs Data In msb t t MDls MDlh MDIDO msb (slave) t MDOf MDODI msb (master) t MSKd ...
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MSK t MSKh t MSKs Data In t MDls MDIDO (slave) t MDOf MDODO (master) MCS (slave) t MCSs Figure 82. Microwire Transaction Timing, Normal Mode, SCIDL = 1 www.national.com t MSKp t MSKh msb t MDlh msb msb 192 ...
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MSKp MSK t MSKs t t MSKh MSKl Data In msb t t MDls MDlh MDIDO msb (slave) t MDOf MDODO msb (master) MCS (slave) t MCSs Figure 83. Microwire Transaction Timing, Alternate Mode, SCIDL = 0 t MSKhd ...
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MSK t MSKs Data In MDIDO (slave) t MDOf MDODI (master) t MCS (slave only) t MCSs Figure 84. Microwire Transaction Timing, Alternate Mode, SCIDL = 1 MSK t MSKs MDODI Dl msb (slave MDls t MITOp MDIDO ...
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ACCESS.BUS TIMING Symbol Figure Description Bus free time between Stop and Start t 87 BUFi Condition t SCL setup time 87 CSTOsi t SCL hold time 87 CSTRhi t SCL setup time 87 CSTRsi t Data High setup time ...
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SDA 0.3VCC 0.7VCC SCL 0.3VCC Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. SDA t DLCs SCL Note: In the timing tables the parameter ...
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SDA t SDAsi SCL t SCAvo t SDAh t CSLlow Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing. unless the parameter already includes the suffix. ...
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USB PORT AC CHARACTERISTICS Symbol Description T Rise Time R T Fall Time F T Fall/Rise Time Matching (T RFM V Output Signal Crossover Voltage CRS Z Driver Output Impedance DRV a. Waveforms measured at 10% to 90%. 27.12 ...
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VERSATILE TIMING UNIT (VTU) TIMING Table 65 Versatile Timing Unit Input Signals Figur Symbol Description e t TIOx Input High Time 90 TIOH t TIOx Input Low Time 90 TIOL CLK TIOx Figure 91. Versatile Timing Unit Input Timing ...
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EXTERNAL BUS TIMING Symbol Figure Description 92, Input Setup Time t 94, 1 D[15:0] 95, 96 92, Output Hold Time t 94, 2 D[15:0] 95, 96 Output Valid Time t 92 D[15:0] 92, Output Valid Time 93, ...