CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 134

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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Power Down
When this device is in Power Save, Idle, or Halt mode, the
ACB module is not active but retains its status. If the ACB is
enabled (ACBCTL2.ENABLE = 1) on detection of a Start
Condition, a wake-up signal is issued to the MIWU module
(see Section 13.0). Use this signal to switch this device to
Active mode.
The ACB module cannot check the address byte for a match
following the start condition that caused the wake-up event
for this device. The ACB responds with a negative acknowl-
edge, and the device should resend both the Start Condition
and the address after this device has had time to wake up.
Check that the ACBCST.BUSY bit is inactive before entering
Power Save, Idle, or Halt mode. This guarantees that the de-
vice does not acknowledge an address sent and stop re-
sponding later.
21.2.3
The SDA and SCL pins are driven as open-drain signals.
For more information, see the I/O configuration section.
21.2.4
The ACB module permits software to set the clock frequen-
cy used for the ACCESS.bus clock. The clock is set by the
ACBCTL2.SCLFRQ field. This field determines the SCL
clock period used by this device. This clock low period may
be extended by stall periods initiated by the ACB module or
by another ACCESS.bus device. In case of a conflict with
another bus master, a shorter clock high period may be
forced by the other bus master until the conflict is resolved.
ACB Clock Frequency Configuration
SDA and SCL Pins Configuration
134
21.3
The ACCESS.bus interface uses the registers listed in
Table 49.
21.3.1
The ACBSDA register is a byte-wide, read/write shift regis-
ter used to transmit and receive data. The most significant
bit is transmitted (received) first and the least significant bit
is transmitted (received) last. Reading or writing to the ACB-
SDA register is allowed when ACBST.SDAST is set; or for
repeated starts after setting the START bit. An attempt to
access the register in other cases produces unpredictable
results.
21.3.2
The ACBST register is a byte-wide, read-only register that
maintains current ACB status. At reset, and when the mod-
ule is disabled, ACBST is cleared.
XMIT
SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT
ACBADDR1
ACBADDR2
7
7
ACBCTL1
ACBCTL2
ACBCTL3
ACBSDA
ACBCST
ACBST
Name
Table 49 ACCESS.bus Interface Registers
ACCESS.BUS INTERFACE REGISTERS
ACB Serial Data Register (ACBSDA)
ACB Status Register (ACBST)
6
The Direction Bit bit is set when the ACB mod-
ule is currently in master/slave transmit mode.
Otherwise it is cleared.
0 – Receive mode.
1 – Transmit mode.
5
FF FECCh
FF FECAh
FF FECEh
FF FEC0h
FF FEC2h
FF FEC4h
FF FEC6h
FF FEC8h
Address
4
DATA
3
ACB Status Register
ACB Control Status
ACB Own Address
ACB Own Address
ACB Serial Data
2
ACB Control
ACB Control
ACB Control
Description
Register 1
Register 2
Register 3
Register 1
Register 2
Register
Register
1
0
0