CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 118

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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ables receive interrupts, without regard to the state of the
UERI bit. However, receive error interrupts should be en-
abled (the UEEI bit is set) to allow detection of receive errors
when DMA is used.
19.2.8
A line break is generated when the UBRK bit is set in the
UMDSL1 register. The TXD line remains low until the pro-
gram resets the UBRK bit.
A line break is detected if RXD remains low for 10 bit times
or longer after a missing stop bit is detected.
19.2.9
Parity is only generated or checked with the 7-bit and 8-bit
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in normal mode with
the 9-bit data format. Parity generation and checking are en-
abled and disabled using the PEN bit in the UFRS register.
The UPSEL bits in the UFRS register are used to select
odd, even, or no parity.
19.3
Software interacts with the UART by accessing the UART
registers. There are eight registers, as listed in Table 45.
UMDSL1
UMDSL2
UICTRL
USPOS
URBUF
UBAUD
UTBUF
USTAT
UOVR
Name
UPSR
UFRS
Break Generation and Detection
Parity Generation and Detection
UART REGISTERS
Table 45 UART Registers
FF FE4Ch
FF FE4Eh
FF FE4Ah
FF FE42h
FF FE40h
FF FE48h
FF FE46h
FF FE44h
FF FE50h
FF FE52h
FF FE54h
Address
UART Interrupt Control
UART Status Register
UART Transmit Data
UART Receive Data
UART Frame Select
UART Mode Select
UART Mode Select
UART Oversample
UART Baud Rate
UART Baud Rate
Position Register
UART Sample
Rate Register
Description
Register 1
Register 2
Prescaler
Register
Register
Divisor
Buffer
Buffer
118
19.3.1
The URBUF register is a byte-wide, read/write register used
to receive each data byte.
19.3.2
The UTBUF register is a byte-wide, read/write register used
to transmit each data byte.
19.3.3
The UPSR register is a byte-wide, read/write register that
contains the 5-bit clock prescaler and the upper three bits of
the baud rate divisor. This register is cleared upon reset.
The register format is shown below.
UPSC
UDIV10:8
19.3.4
The UBAUD register is a byte-wide, read/write register that
contains the lower eight bits of the baud rate divisor. The
register contents are unknown at power-up and are left un-
changed by a reset operation. The register format is shown
below.
UDIV7:0
7
7
7
7
UART Receive Data Buffer (URBUF)
UART Transmit Data Buffer (UTBUF)
UART Baud Rate Prescaler (UPSR)
UART Baud Rate Divisor (UBAUD)
The Prescaler field specifies the prescaler val-
ue used for dividing the System Clock in the
first stage of the two-stage divider chain. For
the prescaler factors corresponding to each 5-
bit value, see Table 44.
The Baud Rate Divisor field holds the three
most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second
stage of the two-stage divider chain. The re-
maining bits of the baud rate divisor are held
in the UBAUD register.
The Baud Rate Divisor field holds the eight
lowest-order bits of the UART baud rate divi-
sor used in the second stage of the two-stage
divider chain. The three most significant bits
are held in the UPSR register. The divisor val-
ue used is (UDIV[10:0] + 1).
UPSC
UDIV7:0
URBUF
UTBUF
3
2
UDIV10:8
0
0
0
0