CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 26

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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6.2
The BIU controls the interface between the CPU core bus
and those on-chip modules which are mapped into BIU
zones. These on-chip modules are the flash program mem-
ory and the I/O zone. The BIU controls the configured pa-
rameters for bus access (such as the number of wait states
for memory access) and issues the appropriate bus signals
for the requested access.
6.3
There are four types of data transfer bus cycles:
The type of data cycle used in a particular transaction de-
pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write
or normal/fast read).
For read operations, a basic normal read takes two clock cy-
cles, and a fast-read bus cycle takes one clock cycle. Nor-
mal read bus cycles are enabled by default after reset.
For write operations, a basic late-write bus cycle takes two
clock cycles, and a basic early-write bus cycle takes three
clock cycles. Early-write bus cycles are enabled by default
after reset. However, late-write bus cycles are needed for
ordinary write operations, so this configuration must be
changed by software (see Section 6.4.1).
In certain cases, one or more additional clock cycles are
added to a bus access cycle. There are two types of addi-
tional clock cycles for ordinary memory accesses, called in-
ternal wait cycles (TIW) and hold (T hold ) cycles.
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request.
A hold cycle is inserted at the end of a bus cycle. This holds
the data on the data bus for an extended number of clock cy-
cles.
Normal read
Fast read
Early write
Late write
BUS INTERFACE UNIT (BIU)
BUS CYCLES
26
6.4
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access-
ing memory. During initialization of the system, these regis-
ters should be programmed with appropriate values so that
the minimum allowable number of cycles is used. This num-
ber varies with the clock frequency.
There are five BIU control registers, as listed in Table 10.
These registers control the bus cycle configuration used for
accessing the various on-chip memory types.
6.4.1
The BCFG register is a byte-wide, read/write register that
selects early-write or late-write bus cycles. At reset, the reg-
ister is initialized to 07h. The register format is shown below.
EWR
At reset, the BCFG register is initialized to 07h, which se-
lects early-write operation. However, late-write operation is
required for normal device operation, so software must
change the register value to 06h. Bits 1 and 2 of this register
must always be set when writing to this register.
7
SZCFG0
SZCFG1
SZCFG2
IOCFG
Name
BCFG
BIU CONTROL REGISTERS
BIU Configuration Register (BCFG)
Table 10 Bus Control Registers
Reserved
The Early Write bit controls write cycle timing.
0
1
–
–
FF F900h
FF F902h
FF F904h
FF F906h
FF F908h
Late-write operation (2 clock cycles to
write).
Early-write operation.
Address
BIU Configuration Register
3
I/O Zone Configuration
Configuration Register
Configuration Register
Configuration Register
Static Zone 0
Static Zone 1
Static Zone 2
Description
2
1
Register
1
1
EWR
0