CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 34

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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USB_ENABLE The USB_ENABLE bit can be used to force
8.4.2
The Protection Word resides in Information Block 1 at ad-
dress 0FEh. At reset, the Protection Word is copied into the
FMAR1 register.
BOOTAREA The BOOTAREA field specifies the size of the
EMPTY
WRPROT RDPROT ISPE
15
13
Protection Word
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the MCFG register (see Section 7.1), and
the USB_ENABLE bit in the Function Word.
0
1
Boot Area. The Boot Area starts at address 0
and ends at the address specified by this field.
The inverted bits of the BOOTAREA field
count the number of 1024-byte blocks to be
reserved as the Boot Area. The maximum
Boot Area size is 7K bytes (address range 0 to
1BFFh). The end of the Boot Area defines the
start of the Code Area. If the device starts in
ISP mode and there is no Boot Area defined
(encoding 111b), the device is kept in reset.
Table 16 lists all possible boot area encod-
ings.
The EMPTY field indicates whether the flash
program memory has been programmed or
should be treated as blank. If a majority of the
three EMPTY bits are clear, the flash program
memory is treated as programmed. If a major-
ity of the EMPTY bits are set, the flash pro-
gram memory is treated as empty. If the
12
BOOT
AREA
–
–
111
110
101
100
011
010
001
000
External USB transceiver forced into low-
power mode.
Transceiver power mode dependent on
USB controller status and programming
of the Function Word.
Table 16 Boot Area Encodings
10
No Boot Area defined
9
Size of the Boot
7
1024 bytes
2048 bytes
3072 bytes
4096 bytes
5120 bytes
6144 bytes
7168 bytes
Area
EMPTY BOOTAREA 1
6
4
3
Code Area
00 0C00h
00 1C00h
00 0000h
00 0400h
00 0800h
00 1000h
00 1400h
00 1800h
Address
Start
1
0
34
ISPE
RDPROT
WRPROT
Not Empty
Not Empty
Not Empty
EMPTY
Empty
Empty
Empty
Table 17 CPU Reset Behavior
ENV[1:0] inputs (see Section 6.1) are sam-
pled high at reset and the EMPTY bits indicate
the flash program memory is empty, the de-
vice will begin execution in ISP mode. The de-
vice enters ISP mode without regard to the
EMPTY status if ENV0 is driven low and
ENV1 is driven high.
The ISPE field indicates whether the Boot
Area is used to hold In-System-Programming
routines or user application routines. If a ma-
jority of the three ISPE bits are set, the Boot
Area holds ISP routines. If majority of the
ISPE bits are clear, the Boot Area holds user
application routines. Table 17 summarizes all
possible EMPTY, ISPE, and Boot Area set-
tings and the corresponding start-up opera-
tion for each combination. In DEV mode, the
EMPTY bit settings are ignored and the CPU
always starts executing from address 0.
The RDPROT field controls the global read
protection mechanism for the on-chip flash
program memory. If a majority of the three
RDPROT bits are clear, the flash program
memory is protected against read access
from the serial debug interface or an external
flash programmer. CPU read access is not af-
fected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.
The WRPROT field controls the global write
protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the se-
No ISP
No ISP
ISPE
ISP
ISP
ISP
ISP
Boot Area
Don’t Care
Don’t Care
Defined
Defined
Defined
Defined
Not
Not
Device starts in IRE/
Device starts in IRE/
Device starts in IRE/
Start-Up Operation
Device starts in ISP
Device starts in ISP
mode and is kept in
Area start address
mode from Code
ERE mode from
Code Area start
ERE mode from
Code Area start
ERE mode from
its reset state
address 0
address
address