CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 136

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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BB
MATCH
GCMTCH
TSDA
TGSCL
The Bus Busy bit indicates the bus is busy. It
is set when the bus is active (i.e., a low level
on either SDA or SCL) or by a Start Condition.
It is cleared when the module is disabled, on
detection of a Stop Condition, or when writing
1 to this bit. See “Usage Hints” on page 138
for a description of the use of this bit. This bit
should be set when either the SDA or SCL sig-
nals are low. This is done by sampling the
SDA and SCL signals continuously and set-
ting the bit if one of them is low. The bit re-
mains set until cleared by a STOP condition or
written with 1.
0 – Bus is not busy.
1 – Bus is busy.
The Address Match bit indicates in slave
mode when ACBADDR.SAEN is set and the
first seven bits of the address byte (the first
byte transferred after a Start Condition)
matches the 7-bit address in the ACBADDR
register, or when ACBADDR2.SAEN is set
and the first seven bits of the address byte
matches the 7-bit address in the ACBADDR2
register. It is cleared by Start Condition or re-
peated Start and Stop Condition (including il-
legal Start or Stop Condition).
0 – No address match occurred.
1 – Address match occurred.
The Global Call Match bit is set in slave mode
when the ACBCTL1.GCMEN bit is set and the
address byte (the first byte transferred after a
Start Condition) is 00h. It is cleared by a Start
Condition or repeated Start and Stop Condi-
tion (including illegal Start or Stop Condition).
0 – No global call match occurred.
1 – Global call match occurred.
The Test SDA bit samples the state of the SDA
signal. This bit can be used while recovering
from an error condition in which the SDA sig-
nal is constantly pulled low by a slave that
went out of sync. This bit is a read-only bit.
Data written to it is ignored.
The Toggle SCL bit enables toggling the SCL
signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the SCL
signal high for one cycle. Writing 1 to TGSCL
when the SDA signal is high is ignored. The bit
is cleared when the clock toggle is completed.
0 – Writing 0 has no effect.
1 – Writing 1 toggles the SDA signal high for
one cycle.
136
21.3.4
The ACBCTL1 register is a byte-wide, read/write register
that configures and controls the ACB module. At reset and
while the module is disabled (ACBCTL2.ENABLE = 0), the
ACBCTL1 register is cleared.
START
STOP
STASTRE NMINTE GCMEN ACK Res. INTEN STOP START
7
ACB Control Register 1 (ACBCTL1)
6
The Start bit is set to generate a Start Condi-
tion on the ACCESS.bus. The START bit is
cleared when the Start Condition is sent, or
upon
(ACBST.BER = 1). This bit should be set only
when in Master mode, or when requesting
Master mode. If this device is not the active
master of the bus (ACBST.MASTER = 0), set-
ting the START bit generates a Start Condition
as soon as the ACCESS.bus is free
(ACBCST.BB = 0). An address send se-
quence should then be performed. If this de-
vice is the active master of the bus
(ACBST.MASTER = 1), when the START bit is
set, a write to the ACBSDA register generates
a Start Condition, then the ACBSDA data is
transmitted as the slave’s address and the re-
quested transfer direction. This case is a re-
peated Start Condition. It may be used to
switch the direction of the data flow between
the master and the slave, or to choose anoth-
er slave device without using a Stop Condition
in between.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Start condition.
The Stop bit in master mode generates a Stop
Condition that completes or aborts the current
message transfer. This bit clears itself after
the the Stop condition is issued.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Stop condition.
5
detection
4
3
of
2
a
Bus
1
Error
0