CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 61

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

13.0 Multi-Input Wake-Up
The Multi-Input Wake-Up Unit (MIWU) monitors its 16 input
channels for a software-selectable trigger condition. On de-
tection of a trigger condition, the module generates an inter-
rupt request and if enabled, a wake-up request. A wake-up
request can be used by the power management unit to exit
the Halt, Idle, or Power Save mode and return to the active
mode. An interrupt request generates an interrupt to the
CPU (interrupt IRQ2–IRQ5), which allows an interrupt han-
dler to respond to MIWU events.
The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the in-
terrupt request associated with the MIWU that gets the CPU
to start executing code, by jumping to the corresponding in-
terrupt handler. Therefore, setting up the MIWU interrupt
handler is essential for any wake-up operation.
There are four interrupt requests that can be routed to the
ICU as shown in Figure 10. Each of the 16 MIWU channels
can be programmed to activate one of these four interrupt
requests.
The MIWU channels are named WUI0 through WUI15, as
shown in Table 28.
Each channel can be configured to trigger on rising or falling
edges, as determined by the setting in the WKEDG register.
Each trigger event is latched into the WKPND register. If a
trigger event is enabled by its respective bit in the WKENA
register, an active wake-up/interrupt signal is generated.
Software can determine which channel has generated the
active signal by reading the WKPND register.
MIWU Channel
WUI10
WUI11
WUI12
WUI13
WUI14
WUI15
WUI0
WUI1
WUI2
WUI3
WUI4
WUI5
WUI6
WUI7
WUI8
WUI9
Table 28 MIWU Sources
USB Wake-Up
Bluetooth LLC
TWM-T0OUT
ACCESS.bus
Reserved
AAI SFS
Source
MWCS
RXD
CTS
PG0
PG1
PG2
PG3
PG6
PG7
PI6
61
The MIWU is active at all times, including the Halt mode. All
device clocks are stopped in this mode. Therefore, detecting
an external trigger condition and the subsequent setting of
the pending bit are not synchronous to the System Clock.
13.1
Table 29 lists the MIWU unit registers.
13.1.1
The WKEDG register is a word-wide read/write register that
controls the edge sensitivity of the MIWU channels. The
WKEDG register is cleared upon reset, which configures all
channels to be triggered on rising edges. The register for-
mat is shown below.
WKED
15
WKICTL1
WKICTL2
WKIENA
WKEDG
WKENA
WKPND
WKPCL
Name
Table 29 Multi-Input Wake-Up Registers
MULTI-INPUT WAKE-UP REGISTERS
Wake-Up Edge Detection Register (WKEDG)
The Wake-Up Edge Detection bits control the
edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI[15:0]
channels, respectively.
0
1
–
–
Triggered on rising edge (low-to-high
transition).
Triggered on falling edge (high-to-low
transition).
FF FC8Ch
FF FC80h
FF FC82h
FF FC84h
FF FC86h
FF FC88h
FF FC8Ah
Address
WKED
Detection Register
Wake-Up Interrupt
Wake-Up Interrupt
Wake-Up Interrupt
Control Register 1
Control Register 2
Wake-Up Pending
Wake-Up Pending
Wake-Up Enable
Enable Register
Wake-Up Edge
Clear Register
Description
Register
Register
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