CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 60

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

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with the wake-up source (MIWU or NMI) that causes pro-
gram execution to resume.
12.7.1
A transition from Active mode to Power Save mode is per-
formed by writing a 1 to the PMMCR.PSM bit. The transition
to Power Save mode is either initiated immediately or at ex-
ecution of the next WAIT instruction, depending on the state
of the PMMCR.WBPSM bit.
For an immediate transition to Power Save mode (PM-
MCR.WBPSM = 0), the CPU continues to operate using the
low-frequency clock. The PMMCR.PSM bit becomes set
when the transition to the Power Save mode is completed.
For a transition at the next WAIT instruction (PM-
MCR.WBPSM = 1), the CPU continues to operate in Active
mode until it executes a WAIT instruction. At execution of
the WAIT instruction, the device enters the Power Save
mode, and the CPU waits for the next interrupt event. In this
case, the PMMCR.PSM bit becomes set when it is written,
even before the WAIT instruction is executed.
12.7.2
Entry into Idle mode is performed by writing a 1 to the PM-
MCR.IDLE bit and then executing a WAIT instruction. The
PMMCR.WBPSM bit must be set before the WAIT instruc-
tion is executed. Idle mode can be entered only from the Ac-
tive mode. The DHC and DMC bits must be set when
entering Idle mode.
12.7.3
When the low-frequency oscillator is used to generate the
Slow Clock, power consumption can be reduced further in
the Power Save mode by disabling the high-frequency oscil-
lator. This is accomplished by writing a 1 to the PM-
MCR.DHC bit before executing the WAIT instruction that
puts the device in the Power Save mode. The high-frequen-
cy clock is turned off only after the device enters the Power
Save mode.
The CPU operates on the low-frequency clock in Power
Save mode. It can turn off the high-frequency clock at any
time by writing a 1 to the PMMCR.DHC bit. The high-fre-
quency oscillator is always enabled in Active mode and al-
ways disabled in Halt mode, without regard to the
PMMCR.DHC bit setting.
Immediately after power-up and entry into Active mode,
software must wait for the low-frequency clock to become
stable before it can put the device in Power Save mode. It
should monitor the PMMSR.OLC bit for this purpose. Once
this bit is set, Slow Clock is stable and Power Save mode
can be entered.
12.7.4
Entry into Halt mode is accomplished by writing a 1 to the
PMMCR.HALT bit and then executing a WAIT instruction.
The PMMCR.WBPSM bit must be set before the WAIT in-
struction is executed. Halt mode can be entered only from
Active mode. The DHC and DMC bits must be set when en-
tering Idle mode.
Active Mode to Power Save Mode
Disabling the High-Frequency Clock
Entering Idle Mode
Entering Halt Mode
60
12.7.5
A transition from Power Save mode to Active mode can be
accomplished by either a software command or a hardware
wake-up event. The software method is to write a 0 to the
PMMCR.PSM bit. The value of the register bit changes only
after the transition to the Active mode is completed.
If the high-frequency oscillator is disabled for Power Save
operation, the oscillator must be enabled and allowed to sta-
bilize before the transition to Active mode. To enable the
high-frequency oscillator, software writes a 0 to the PM-
MCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit,
software must first monitor the PMMSR.OMC bit to deter-
mine when the oscillator has stabilized.
12.7.6
A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to Active mode. Hardware
wake-up events are:
When a wake-up event occurs, the on-chip hardware per-
forms the following steps:
12.7.7
The Power Management Module has several mechanisms
to protect the device from malfunctions caused by missing
or unstable clock signals.
The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits
indicate the current status of the PLL, high-frequency oscil-
lator, and low-frequency oscillator, respectively. Software
can check the appropriate bit before switching to a power
mode that requires the clock. A set status bit indicates an
operating, stable clock. A clear status bit indicates a clock
that is disabled, not available, or not yet stable. (Except in
the case of the PLL, which has a set status bit when dis-
abled.)
During a power mode transition, if there is a request to
switch to a mode with a clear status bit, the switch is delayed
until that bit is set by the hardware.
When the system is built without an external crystal network
for the low-frequency clock, Main Clock is divided by a pres-
caler factor to produce the low-frequency clock. In this situ-
ation, Main Clock is disabled only in the Idle and Halt
modes, and cannot be disabled for the Power Save mode.
Without an external crystal network for the low-frequency
clock, the device comes out of Halt or Idle mode and enters
Active mode with Main Clock driving Slow Clock.
Note: For correct operation in the absence of a low-fre-
quency crystal, X2CKI must be tied low (not left floating) so
that the hardware can detect the absence of the crystal.
1. Clears the PMMCR.DMC bit, which enables the high-
2. Waits for the PMMSR.OMC bit to become set, which in-
3. Clears the PMMCR.DHC bit, which enables the PLL.
4. Waits for the PMMSR.OHC bit to become set.
5. Switches the device into Active mode.
Non-Maskable Interrupt (NMI)
Valid wake-up event on a Multi-Input Wake-Up channel
frequency clock (if it was disabled).
dicates that the high-frequency clock is operating and
is stable.
Software-Controlled Transition to Active Mode
Wake-Up Transition to Active Mode
Power Mode Switching Protection