DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 13

• Manufacturer Part Number: DJLXT360LE.A2 S E001
• Manufacturer: Intel

Specifications of DJLXT360LE.A2 S E001

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output.
2. Midrange is a voltage level such that 2.3 V
PLCC
27
28
10
Table 3. LXT360 Signal Descriptions (Continued)
Pin #
1, 6, 8,
12, 14,
17, 22,
23, 26,
28, 30,
33, 34,
40, 44
9, 11,
QFP
37
38
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360
TAOS/QRSS/ CLKE
LLOOP/SCLK
Symbol
n/c
I/O
DI
DI
-
Midrange
1
HARDWARE MODES:
Local Loopback. When held High, the data on TPOS and TNEG loops
back digitally to the RPOS and RNEG outputs (through the JA if enabled).
Connecting this pin to Midrange
TRING are looped back to RTIP and RRING).
HOST MODES:
Serial Clock. SCLK synchronizes serial port read/write operations. The
clock frequency can be any rate up to 2.048 MHz.
HARDWARE MODES:
Transmit All Ones. When held High, the transmit data inputs are ignored
and the LXT360 transmits a stream of 1’s at the TCLK frequency. If TCLK
is not supplied, MCLK becomes the transmit clock reference. Note that
TAOS is inhibited during Remote loopback.
QRSS. In QRSS mode, setting this pin to Midrange
pattern generation and detection. The transceiver transmits the QRSS
pattern at the TCLK rate (or MCLK, if TCLK is not present).
HOST MODES:
Clock Edge Select. When CLKE is High, RPOS/RNEG or RDATA are
valid on the falling edge of RCLK, and SDO is valid on the rising edge of
SCLK.
When CLKE is Low, RPOS/RNEG or RDATA are valid on the rising edge of
RCLK, and SDO is valid on the falling edge of SCLK. The operation of
CLKE is summarized in
Not Connected
2.7 V. Midrange may also be established by letting the pin float.
Table 4 on page
Description
2
enables Analog loopback (TTIP and
18.
2
, enables QRSS
13