DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 42

DJLXT360LE.A2 S E001

Manufacturer Part Number
DJLXT360LE.A2 S E001
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT360LE.A2 S E001

Number Of Transceivers
1
Operating Supply Voltage (typ)
5V
Screening Level
Industrial
Mounting
Surface Mount
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
42
Total
power
dissipation
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level input voltage
Midrange input voltage
Low level input voltage
Input leakage current
Three-state leakage current
TTIP/TRING leakage current (pins 13, 16)
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. TVCC and VCC must not differ by more than 0.3 V.
3. Power dissipation while driving 100
4. Power dissipation while driving 100
5. Power dissipation while driving 120
1. Functionality of pins 23 and 25 depend on mode. See Host mode and Hardware mode description.
2. Output drivers will output CMOS logic levels into CMOS loads.
3. As an alternative to supplying 2.3 - 2.7 V (Midrange logic level) to these pins, they may be left open.
4. Referenced pin numbers are for the PLCC package. Refer to
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load. This implementation has better return loss performance and is less sensitive to changes in impedances
variations.
power dissipation on device and load. Digital levels are within 10% of the supply rails and digital outputs driving a 50 pF
capacity load.
Table 26. Recommended Operating Conditions (Continued)
Table 27. Digital Characteristics
Parameter
low power
standard
power
E1
T1
T1
1,2
3
3
3
4
5
1,2
3
1,2
(pins 5, 9, 11, 26-28)
(pins 5, 9, 11, 26-28)
1,2
(pins 5, 9, 11, 26-28)
(pins 1-4, 17, 23-25)
(pins 1-4, 17, 23-25)
Parameter
(pins 6-8, 10, 12, 23, 25)
(pins 6-8, 10, 12, 23, 25)
1
(all outputs)
Short Haul/
Short Haul
Short Haul
Long Haul
Long Haul
Long Haul
load coupled through 1:1.15 transformer and 0
load coupled through 1:2 transformer and 9.1
load coupled through 1:2 transformer and 9.1
4
4
4
4
4
4
Sym
P
P
P
P
P
P
P
P
P
P
D
D
D
D
D
D
D
D
D
D
4
4
Host mode
Hardware
mode
Min
Figure 2 on page 8
Sym
V
V
V
V
V
V
V
V
I
I
I
3
TR
OH
LL
OL
IM
IH
IH
Typ
IL
IL
IL
310
225
245
195
470
320
350
260
275
215
L
1
Min
2.0
2.4
3.5
2.3
0
0
Max
380
295
325
265
560
380
420
310
330
270
for the corresponding QFP pins.
Typ
resistor on TTIP/TRING. Includes
resistor on TTIP/TRING. Includes
resistor on TTIP/TRING. Includes
Unit
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Max
±1.2
±50
±10
0.8
0.4
2.7
0.8
1.5
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
100% mark density
50% mark density
Unit
mA
Test Conditions
V
V
V
V
V
V
V
V
A
A
I
I
in Idle and
Power Down
OUT
OUT
Conditions
Datasheet
Test
= 400 A
= 1.6 mA

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