DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 18

• Manufacturer Part Number: DJLXT360LE.A2 S E001
• Manufacturer: Intel

Specifications of DJLXT360LE.A2 S E001

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.6.1
18
Table 4.
Figure 4
composed of an 8-bit Command/Address byte (bits R/ W and A1-A7) and a subsequent 8-bit data
byte (bits D0-7). The R/W bit commands a read or a write operation, i.e., the direction of the
following byte. Bits A1 through A6, of the command/address byte, point to a specific register. Note
that the LXT360 address decoder ignores bits A0 and A7. Refer to
specifications.
Host mode also allows control of data output timing. The CLKE pin determines when SDO is
valid, relative to the Serial Clock (SCLK) as shown in
Interrupt Handling
In Host mode, the LXT360 provides a latched interrupt output pin (INT). When enabled, a change
in any of the Performance Status Register bits will generate an interrupt. An interrupt can also be
generated when the elastic store overflows (TSR.ESOVR) or underflows (TSR.ESUNF). When an
interrupt occurs, the INT output pin is pulled Low. Note that the output stage of the INT pin has
internal pull-down only. Therefore, each device that shares the INT line requires an external
pull-up resistor.
The interrupt is cleared when the interrupt condition no longer exists, and the host processor writes
a 1 to the respective interrupt causing bit(s) in the Interrupt Clear Register (ICR). Leaving a 1 in
any of the ICR bits masks that interrupt. To re-enable an interrupt bit, write a 0.
CLKE Pin Settings
1. The clock edge selection feature is not available in Hardware
mode.
CLKE
High
Low
Pin
shows the serial port data structure. The registers are accessible through a 16-bit word
Output
RDATA
RDATA
RPOS
RNEG
RPOS
RNEG
SDO
SDO
1
Falling SCLK
Falling RCLK
Rising RCLK
Rising SCLK
Valid Clock
Edge
Table
4.
Table 35 on page 48
Datasheet
for timing