DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 28

• Manufacturer Part Number: DJLXT360LE.A2 S E001
• Manufacturer: Intel

Specifications of DJLXT360LE.A2 S E001

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.7.4.2
2.7.4.3
2.7.4.4
2.7.5
2.7.5.1
2.7.5.2
28
Alarm Indication Signal Detection (AIS)
This function is only available in Host mode. The receiver detects an AIS pattern when it receives
fewer than three 0s in any string of 2048 bits. The device clears the AIS condition when it receives
three or more 0s in a string of 2048 bits.
The AIS bit in the Performance Status Register indicates AIS detection. Whenever the AIS status
changes, bit TSR.TAIS =1. Unless masked, a change of AIS status generates an interrupt.
Driver Failure Monitor Open (DFMO)
This function is only available in Host mode. The DFMO bit is available in the Performance Status
Register to indicate an open condition on the lines. DFMO can generate an interrupt to the host
controller. The Transition Status Register bit TDFMO indicates a transition in the status of the bit.
Writing a 1 to ICR.CDFMO will clear or mask the interrupt.
Elastic Store Overflow/Underflow (ESOVR and ESUNF)
This function is only available in Host mode. When the bit count in the Elastic Store (ES) is within
two bits of overflowing or underflowing the ES adjusts the output clock by
ES provides an indication of overflow and underflow via bits TRS.ESOVR and TSR.ESUNF.
These are “sticky bits” and will stay set to 1 until the host controller reads the register. These
interrupts can be cleared or masked by writing a 1 to the bits ICR.CESO and ICR.CESU,
respectively.
Other Diagnostic Reports
Receive Line Attenuation Indication
This function is only available in Host mode. The Equalizer Status Register (ESR) provides an
approximation of the line attenuation encountered by the device. The four MSBs of the register
(ESR.LATN7:4) indicate line attenuation in approximately 2.9 dB steps for both T1 and E1
operation of the receive equalizer. For instance, if ESR.LATN7:4 is 10 (decimal), then the receiver
is seeing a signal attenuated by approximately 29 dB (2.9 dB x 10) of cable loss.
Built-In Self Test (BIST)
The BIST function in only available in Host mode. The BIST exercises the internal circuits by
providing an internal QRSS pattern, running it through the encoders and the transmit drivers then
looping it back through the receive equalizer, jitter attenuator and decoders to the QRSS pattern
detection circuitry. The BIST is initiated by setting bit CR3.SBIST = 1. If all the blocks in this data
path operate correctly, the receive pattern detector locks onto the pattern. It then pulls INT Low and
sets the following bits:
The QPD pin also indicates completion status of the test. Initiating the BIST forces QPD High.
During the test, it remains High until the test finishes successfully, at which time it goes Low. Note
that during BIST, the TPOS/TNEG inputs must remain at logic level = 0
•
•
•
TSR.TQRSS = 1
PSR.QRSS = 1
PSR.BIST = 1
1
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8
of a bit period. The
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