DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 16

• Manufacturer Part Number: DJLXT360LE.A2 S E001
• Manufacturer: Intel

Specifications of DJLXT360LE.A2 S E001

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

LXT360 — Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
2.3
2.3.1
2.3.2
2.3.3
2.3.4
16
Receiver
A 1:1 transformer provides the interface to the twisted-pair line (RTIP/RING). Recovered data is
output at RPOS/RNEG (RDATA in Unipolar mode), and the recovered clock is output at RCLK.
Refer to
Receive Equalizer
The receive equalizer processes the signal received at RTIP and RRING. The equalizer gain is up
to 43 dB in E1 long-haul applications and 36 dB for T1 applications. As shown in
Equalizer Control inputs (EC1 through EC4) determine the maximum gain applied to the equalizer.
In Host mode, EC1 through 4 are established by bits 0 through 3 of Control Register #1 (CR1),
respectively. In Hardware mode, pins EC1, EC2, EC3, and EC4 specify equalizer gain setting.
With EC1 Low, up to 36 dB of gain may be applied. When EC1 is High, 26 dB is the gain limit to
provide an increased noise margin in shorter loop operations.
Receive Data Recovery
The transceiver filters the equalized signal and applies it to the peak detector and data slicers. The
peak detector samples the inputs and determines the maximum value of the received signal. The
data slicers are set at 50% of the peak value to ensure optimum signal-to-noise performance.
After processing through the data slicers, the received signal goes to the data and timing recovery
section, then to the B8ZS/HDB3 decoder (if selected) and to the receive monitor. The data and
timing recovery circuits provide input jitter tolerance significantly better than required by AT&T
Pub 62411 and ITU G.823. See
Receive Digital Data Interface
Recovered data is routed to the Loss of Signal (LOS) Monitor. In Host mode, it also goes through
the Alarm Indication Signal (AIS, Blue Alarm) Monitor. The jitter attenuator (JA) may be enabled
or disabled in the receive data path or the transmit path. Received data may be routed to either the
B8ZS or HDB3 decoder or neither. Finally, the device may send the digital data to the framer as
either unipolar or bipolar data.
When decoding unipolar data to the framer, the LXT360 reports reception of bipolar violations by
driving the BPV pin High. During E1 operation in Host mode, the device can be programmed to
report HDB3 code violations and Zero Substitution Violations on the BPV pin. See
Mode Operation” on page 20
Receiver Monitor Mode
The receive equalizer can be used in Monitor mode applications. Monitor mode applications
require 20 dB to 30 dB resistive attenuation of the signal, plus a small amount of cable attenuation
(less than 6 dB). In Host mode, setting bit CR3.EQZMON = 1 configures the device to operate in
Monitor mode. Note that the LXT360 must be in T1/E1 long-haul receiver mode (set bits
CR1.EC4:1 = 0xx0, 1001, or 1010) to enable Monitor mode. Note that the Monitor mode feature is
not available in Hardware mode.
In Monitor mode, the receive equalizer will handle signals attenuated resistively by 20 to 30 dB,
along with 0 to 6 dB of cable attenuation for both E1 and T1 applications.
Table 33 on page 47
for receiver timing specifications.
for details.
“Test Specifications” on page 41
for details.
Table
“Diagnostic
Datasheet
10,