DJLXT360LE.A2 S E001 Intel, DJLXT360LE.A2 S E001 Datasheet - Page 23

• Manufacturer Part Number: DJLXT360LE.A2 S E001
• Manufacturer: Intel

Specifications of DJLXT360LE.A2 S E001

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

2.7.1.3
2.7.1.4
2.7.1.5
Datasheet
Figure 8. Remote Loopback
Remote Loopback (RLOOP)
See
and TPOS/TNEG or TDATA), and bypasses the in-line encoders/decoders. The RPOS/RNEG or
RDATA outputs loop back through the transmit circuits to TTIP and TRING at the RCLK
frequency. The RLOOP command does not affect the receiver circuits which continue to output the
RCLK and RPOS/RNEG or RDATA signals received from the twisted-pair line.
In Host mode, command RLOOP by writing a 1 to bit CR2.ERLOOP. In Hardware mode, RLOOP
is commanded by setting the RLOOP pin High.
Network Loopback (NLOOP)
NLOOP can be initiated only when the Network loopback detect function is enabled. With NLOOP
detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable, 001 = disable)
in the input data stream. The LXT360 responds to both framed and unframed NLOOP patterns.
When the receiver detects the NLOOP enable data pattern repeated for a minimum of five seconds,
loopback is activated. Once activated, operation is identical to Remote loopback (RLOOP).
In Host mode, setting bit CR2.ENLOOP = 1 enables NLOOP detection. In Hardware mode, setting
the RLOOP pin to Midrange enables NLOOP detection.
NLOOP is disabled upon reception of the 001 pattern for five seconds, or by activating RLOOP or
ALOOP, or by disabling NLOOP detection. Note that the LXT360 enters Dual loopback mode
(DLOOP) when both NLOOP and LLOOP functions are selected.
Dual Loopback (DLOOP)
See
High. In Host mode set bits CR2.ERLOOP = 1 and CR2.ELLOOP = 1. In DLOOP mode, the
transmit clock and data inputs (TCLK and TPOS/TNEG or TDATA) loop back through the Jitter
Attenuator (unless disabled) to RCLK and RPOS/RNEG or RDATA. The data and clock recovered
from the twisted-pair line loop back through the transmit circuits to TTIP and TRING without jitter
attenuation.
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications — LXT360
Figure
Figure
8. When RLOOP is active, the device ignores the transmit data and clock inputs (TCLK
9. In Hardware mode, DLOOP is selected by setting both the RLOOP and LLOOP pins
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