MT46H16M32LFCM-6:B Micron Technology Inc, MT46H16M32LFCM-6:B Datasheet - Page 6

• Manufacturer Part Number: MT46H16M32LFCM-6:B
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H16M32LFCM-6:B

• Organization: 16Mx32
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 115mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

List of Figures
Figure 1: 512Mb Mobile LPDDR Part Numbering ............................................................................................. 2
Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9
Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10
Figure 4: 60-Ball VFBGA – 8mm x 9mm (Top View) ......................................................................................... 11
Figure 5: 90-Ball VFBGA – 10mm x 13mm and 9mm x 13mm (Top View) ......................................................... 12
Figure 6: 60-Ball VFBGA (8mm x 9mm) .......................................................................................................... 15
Figure 7: 90-Ball VFBGA (10mm x 13mm) ....................................................................................................... 16
Figure 8: 90-Ball VFBGA (9mm x 13mm) ......................................................................................................... 17
Figure 9: Typical Self Refresh Current vs. Temperature ................................................................................... 25
Figure 10: ACTIVE Command ........................................................................................................................ 37
Figure 11: READ Command ........................................................................................................................... 38
Figure 12: WRITE Command ......................................................................................................................... 39
Figure 13: PRECHARGE Command ................................................................................................................ 40
Figure 14: DEEP POWER-DOWN Command .................................................................................................. 41
Figure 15: Simplified State Diagram ............................................................................................................... 47
Figure 16: Initialize and Load Mode Registers ................................................................................................. 49
Figure 17: Alternate Initialization with CKE LOW ............................................................................................ 50
Figure 18: Standard Mode Register Definition ................................................................................................ 51
Figure 19: CAS Latency .................................................................................................................................. 54
Figure 20: Extended Mode Register ................................................................................................................ 55
Figure 21: Status Read Register Timing .......................................................................................................... 57
Figure 22: Status Register Definition .............................................................................................................. 58
Figure 23: READ Burst ................................................................................................................................... 61
Figure 24: Consecutive READ Bursts .............................................................................................................. 62
Figure 25: Nonconsecutive READ Bursts ........................................................................................................ 63
Figure 26: Random Read Accesses ................................................................................................................. 64
Figure 27: Terminating a READ Burst ............................................................................................................. 65
Figure 28: READ-to-WRITE ............................................................................................................................ 66
Figure 29: READ-to-PRECHARGE .................................................................................................................. 67
Figure 30: Data Output Timing –
Figure 31: Data Output Timing –
Figure 32: Data Output Timing –
Figure 33: Data Input Timing ......................................................................................................................... 72
Figure 34: Write – DM Operation ................................................................................................................... 73
Figure 35: WRITE Burst ................................................................................................................................. 74
Figure 36: Consecutive WRITE-to-WRITE ....................................................................................................... 75
Figure 37: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75
Figure 38: Random WRITE Cycles .................................................................................................................. 76
Figure 39: WRITE-to-READ – Uninterrupting ................................................................................................. 77
Figure 40: WRITE-to-READ – Interrupting ...................................................................................................... 78
Figure 41: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 79
Figure 42: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 80
Figure 43: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81
Figure 44: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 82
Figure 45: Bank Read – With Auto Precharge .................................................................................................. 85
Figure 46: Bank Read – Without Auto Precharge ............................................................................................. 86
Figure 47: Bank Write – With Auto Precharge .................................................................................................. 87
Figure 48: Bank Write – Without Auto Precharge ............................................................................................. 88
Figure 49: Auto Refresh Mode ........................................................................................................................ 89
Figure 50: Self Refresh Mode ......................................................................................................................... 91
PDF: 09005aef82d5d305
512mb_ddr_mobile_sdram_t47m.pdf – Rev. I 12/09 EN
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QH, and Data Valid Window (x16) ................................................... 68
QH, and Data Valid Window (x32) ................................................... 69
DQSCK .......................................................................................... 70
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512Mb: x16, x32 Mobile LPDDR SDRAM
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