MT48LC16M16A2P-7E:D Micron Technology Inc, MT48LC16M16A2P-7E:D Datasheet - Page 49

• Manufacturer Part Number: MT48LC16M16A2P-7E:D
• Description: SDRAM 256MB, SMD, 48LC16, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-7E:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
22. V
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
24. Auto precharge mode only. The precharge timing budget (
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and
33. CKE is HIGH during refresh command period
34. The -6 speed grade does not support CL = 2.
cannot be greater than one-third of the cycle rate. V
a pulse width ≤ 3ns.
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including
used to reduce the data rate.
7ns after the first clock delay, after the last WRITE is executed.
t
t
limit is actually a nominal value and does not result in a fail value.
AC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.
CK = 6ns.
IH
overshoot: V
IH
(MAX) = V
t
CK = 7.5ns; for -7E, CL = 2 and
49
DD
Q + 2V for a pulse width ≤ 3ns, and the pulse width
t
WR, and PRECHARGE commands). CKE may be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RFC (MIN) else CKE is LOW. The I
t
CK = 7.5ns; for -6, CL = 3 and
IL
64Mb: x4, x8, x16 SDRAM
undershoot: V
t
RP) begins 6ns/7ns/7.5ns/
©2000 Micron Technology, Inc. All rights reserved.
IL
(MIN) = –2V for
Notes
DD
6