MT48LC16M16A2P-7E:D Micron Technology Inc, MT48LC16M16A2P-7E:D Datasheet - Page 62

• Manufacturer Part Number: MT48LC16M16A2P-7E:D
• Description: SDRAM 256MB, SMD, 48LC16, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-7E:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

Figure 47:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
DQML, DQMH
COMMAND
A0-A9, A11
BA0, BA1
DQM /
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
WRITE – Without Auto Precharge
ACTIVE
T0
ROW
ROW
BANK
t CKH
t CMH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between <D
3. x16: A8, A9 and A11 = “Don’t Care”
NOP
frequency.
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
DISABLE AUTO PRECHARGE
t CMS
t CL
t DS
COLUMN m 3
WRITE
T2
BANK
D
IN
t CMH
t CH
t DH
m
t DS
D
T3
IN
NOP
m + 1
t DH
62
t DS
IN
D
m> and the PRECHARGE command, regardless of
IN
T4
NOP
m + 2
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t DS
D
IN
NOP
T5
m + 3
t DH
t WR
SINGLE BANK
PRECHARGE
ALL BANKS
2
BANK
T6
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
NOP
t RP
T7
Timing Diagrams
ACTIVE
ROW
ROW
BANK
T8
DON’T CARE