AD7878SQ Analog Devices Inc, AD7878SQ Datasheet - Page 3

• Manufacturer Part Number: AD7878SQ
• Description: IC ADC 12BIT W/DSP INT 28-CDIP
• Manufacturer: Analog Devices Inc

Specifications of AD7878SQ

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Data Interface: DSP
• Number Of Converters: 1
• Power Dissipation (max): 95.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 28-CDIP (0.600", 15.24mm)

TIMING CHARACTERISTICS
Parameter (L Grade)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Specifications subject to change without notice.
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7878 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
l
2
3
4
5
6
7
8
9
10
11
12
13
14
RESET
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25 C to ensure compliance. All input signals are specified with
t
t
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
9
10
2
3
2
and t
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
a. High-Z to V
a. V
14
Figure 2. Load Circuits for Output Float Delay
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
OH
Figure 1. Load Circuits for Access Time
Limit at T
65
65
2 CLK IN Cycles
0
0
45
50
16
0
41
5
45
42
50
20
10
41
2 CLK IN Cycles
to High-Z
OH
MIN
, T
MAX
Limit at T
(J, K, A, B Grades)
65
65
2 CLK IN Cycles
0
0
60
50
16
0
57
5
45
42
50
20
10
57
2 CLK IN Cycles
1
b. V
(V
b. High-Z to V
MIN
DD
OL
= 5 V
, T
to High-Z
MAX
5%, V
Limit at T
(S Grade)
75
75
2 CLK IN Cycles
0
0
60
50
16
0
57
5
45
55
50
30
10
57
2 CLK IN Cycles
OL
CC
= 5 V
–3–
MIN
, T
ABSOLUTE MAXIMUM RATINGS*
(T
V
V
V
V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
Digital Inputs to DGND
Digital Outputs to DGND
Data Pins
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . 1000 mW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability
DD
CC
SS
DD
IN
5%, V
A
MAX
DB11–DB0 . . . . . . . . . . . . . . . . . . . . –0.3 V to V
J, K, L Versions . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –25 C to +85 C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to +125 C
Derates above +75 C by . . . . . . . . . . . . . . . . . . 10 mW/ C
CLK IN, DMWR, DMRD, RESET,
CS, CONVST, ADD0 . . . . . . . . . . . . –0.3 V to V
ALFL, BUSY . . . . . . . . . . . . . . . . . . –0.3 V to V
= +25 C unless otherwise stated)
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to V
SS
Units
ns max CLK IN to BUSY Low Propagation Delay
ns max CLK IN to BUSY High Propagation Delay
min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
min
s max
s max
CC
= –5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Conditions/Comments
CONVST Pulse Width
CS to DMRD/REGISTER ENABLE Setup Time
CS to DMRD/ REGISTER ENABLE Hold Time
DMRD Pulse Width
ADD0 to DMRD/REGISTER ENABLE Setup Time
ADD0 to DMRD/REGISTER ENABLE Hold Time
Data Access Time after DMRD
Bus Relinquish Time
REGISTER ENABLE Pulse Width
Data Valid to REGISTER ENABLE Setup Time
Data Hold Time after REGISTER ENABLE
Data Access Time after BUSY
RESET Pulse Width
5%)
WARNING!
ESD SENSITIVE DEVICE
AD7878
DD
DD
DD
DD
+0.3 V
+0.3 V
+0.3 V
+0.3 V
DD