MAX1358BETL+ Maxim Integrated Products, MAX1358BETL+ Datasheet - Page 31

• Manufacturer Part Number: MAX1358BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1358BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
An internal oscillator and an FLL are used to generate a
4.9152MHz ±1% high-frequency clock. This clock and
derivatives are used internally by the ADC, analog
switches, and PWM. This clock signal outputs to CLK.
When the FLL is enabled, the high- frequency clock is
16-Bit, Data-Acquisition System with ADC, DACs,
Figure 9. 32kHz Crystal-Oscillator Block Diagram
Figure 11. Watchdog Timer Block Diagram
UPIOs, RTC, Voltage Monitors, and Temp Sensor
32KOUT
32KIN
32K
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
______________________________________________________________________________________
WDE
High-Frequency Clock
OSCILLATOR
32.768kHz OSCILLATOR
OSCE
32kHz
BY-8192
DIVIDE-
WDW
POR
Watchdog
4Hz
32K
D
CK
R
Q
Q
locked to the 32.768kHz reference. If the FLL is dis-
abled, the high-frequency clock is free-running. At
power-up, the CLK pin defaults to a 2.4576MHz clock
output, which is compatible with most µCs. See Figure
12 for a block diagram of the high-frequency clock.
The MAX1358B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DV
or CPOUT. See the UPIO__CTRL Register and
UPIO_SPI Register sections for more details on config-
uring the UPIO_ pins.
Figure 10. CLK32K I/O Block Diagram
CLK32K
32K
DD
. UPIO_ outputs can be referenced to DV
CK
D
R
CK32E
Q
Q
OSCE
IO32E
WATCHDOG TIMER
IO32E
User-Programmable I/Os
CLK32K I/O CONTROL
WDTO
IO32E
0
1
MUX
2:1
M32K
DD
31