MAX1358BETL+ Maxim Integrated Products, MAX1358BETL+ Datasheet - Page 52

• Manufacturer Part Number: MAX1358BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1358BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The UPIO1_CTRL register configures the UPIO1 pin
functionality.
UP1MD<3:0>: UPIO1-mode selection bits. These bits
configure the mode for the UPIO1 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP1: Pullup UPIO1 control bit. Set PUP1 = 1 to enable
a weak pullup resistor on the UPIO1 pin, and set PUP1
= 0 to disable it. The pullup resistor is connected to
either DV
The pullup is enabled only when UPIO1 is configured as
an input. Open-drain behavior can be simulated at
UPIO1 by setting the mode to GPO with LL1 = 0 and by
changing the mode to GPI with PUP1 = 0, allowing
external high pullup. The power-on default is 1.
SV1: Supply-voltage UPIO1 selection bit. Set SV1 = 0
to select DV
and set SV1 = 1 to select CPOUT as the supply volt-
16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
The UPIO2_CTRL register configures the UPIO2 pin
functionality.
UP2MD<3:0>: UPIO2-mode selection bits. These bits
configure the mode for the UPIO2 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP2: Pullup UPIO2 control bit. Set PUP2 = 1 to enable
a weak pullup resistor on the UPIO2 pin, and set PUP2
= 0 to disable it. The pullup resistor is connected to
either DV
The pullup is enabled only when UPIO2 is configured as
an input. Open-drain behavior can be simulated at
UPIO2 by setting the mode to GPO with LL2 = 0 and by
changing the mode to GPI with PUP2 = 0, allowing
external high pullup. The power-on default is 1.
SV2: Supply-voltage UPIO2 selection bit. Set SV2 = 0
to select DV
and set SV2 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO2 pin. The power-on default is 0.
UPIO2_CTRL Register (Power-On State: 0000 1000)
UPIO1_CTRL Register (Power-On State: 0000 1000)
52
UP2MD3
UP1MD3
______________________________________________________________________________________
MSB
MSB
DD
DD
DD
DD
or CPOUT as programmed by the SV1 bit.
or CPOUT as programmed by the SV2 bit.
as the supply voltage for the UPIO1 pin,
as the supply voltage for the UPIO2 pin,
UP2MD2
UP1MD2
UP2MD1
UP1MD1
UP2MD0
UP1MD0
age. The selected supply voltage applies to all modes
for the UPIO1 pin. The power-on default is 0.
ALH1: Active logic-level assertion high UPIO1 bit. Set
ALH1 = 0 to define the input or output assertion level
for UPIO1 as low except when in GPI and GPO modes.
Set ALH1 = 1 to define the input or output assertion
level as high. For example, asserting ALH1 defines the
UPIO1 output signal as ALARM, while deasserting
ALH1 defines it as ALARM. Similarly, asserting ALH1
defines the UPIO1 input signal as WU, while deassert-
ing ALH1 defines it as WU. The power-on default is 0.
LL1: Logic-level UPIO1 bit. When UPIO1 is configured
as GPO, LL1 = 0 sets the output to a logic-low and LL1
= 1 sets the output to a logic-high. A read of LL1
returns the voltage level at the UPIO1 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
ALH2: Active logic-level assertion high UPIO2 bit. Set
ALH2 = 0 to define the input or output assertion level
for UPIO2 as low except when in GPI and GPO modes.
Set ALH2 = 1 to define the input or output assertion
level as high. For example, asserting ALH2 defines the
UPIO2 output signal as ALARM, while deasserting
ALH2 defines it as ALARM. Similarly, asserting ALH2
defines the UPIO2 input signal as WU, while deassert-
ing ALH2 defines it as WU. The power-on default is 0.
LL2: Logic-level UPIO2 bit. When UPIO2 is configured
as GPO, LL2 = 0 sets the output to a logic-low and LL2
= 1 sets the output to a logic-high. A read of LL2
returns the voltage level at the UPIO2 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
PUP2
PUP1
SV2
SV1
ALH2
ALH1
LSB
LSB
LL2
LL1