MAX1358BETL+ Maxim Integrated Products, MAX1358BETL+ Datasheet - Page 53

• Manufacturer Part Number: MAX1358BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1358BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-Bit, Data-Acquisition System with ADC, DACs,
Table 16. UPIO Mode Configuration
Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together.
UP2MD<3:0>, UP1MD<3:0>
UPIOs, RTC, Voltage Monitors, and Temp Sensor
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
UP4MD<3:0>,
UP3MD<3:0>,
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
______________________________________________________________________________________
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AL_DAY or
SPDT1 or
SPDT2 or
SLEEP or
SHDN or
DRDY or
PWM or
SWA or
SWB or
WU or
Reserved
Reserved
MODE
GPO
GPI
General-purpose digital input. Active edges detected by UPR_ or UPF_
status register bits. ALH_ has no effect with this setting.
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no
effect with this setting.
Digital input. DAC A buffer switch control. See the SWA bit description in
the SW_CTRL Register section.
Digital input. DAC B buffer switch control. See the SWB bit description in
the SW_CTRL Register section.
Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the
SW_CTRL Register section.
Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the
SW_CTRL Register section.
Sleep-mode digital input. Overrides power-control register and puts the
part into sleep mode when asserted. The clock buffers must be powered
down separately. When deasserted, power mode is determined by the
SHDN bit.
Wake-up digital input. Asserted edge clears SHDN bit.
Reserved. Do not use these settings.
PWM digital output. Signal defined by the PWM_CTRL register. PWM on
(or high or “1”); assertion level defined by the ALH_ bit. When PWM is
disabled (PWME = 0), the UPIO pin idles high (DV
ALH = 1, and low (DGND) if ALH = 0.
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on
default of GPI with pullup ensures initial power-supply turn-on when UPIO
is connected to a power supply with a
RTC alarm digital output. Asserts for time-of-day alarm events; equivalent
to ALD in STATUS register.
Reserved. Do not use these settings.
ADC data-ready digital output. Asserts when analog-to-digital conversion
or calibration completes. Not masked by MADD bit.
DESCRIPTION
input.
DD
or CPOUT) if
53