PSD835G2V-12U STMicroelectronics, PSD835G2V-12U Datasheet

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... Standby current as low as 25 µA ■ Memory speed – Flash memory and SRAM access time for V CC – 120 ns Flash memory and SRAM access time for V CC ® ■ ECOPACK package Doc ID 10585 Rev 3 PSD835G2V LQFP80 (U) = 3 3.0 to 3.6 V 1/120 www.st.com 1 ...

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... Memory Block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 Upper and lower block in main Flash sector . . . . . . . . . . . . . . . . . . . . . . . 33 2/120 First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inventory build-up of preprogrammed devices . . . . . . . . . . . . . . . . . . . . 11 Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 12 Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Separate program and data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 6.5 Ready/Busy (PE4 6.6 Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 Power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 Read Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 Read Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 Read Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.6 Read the Erase/Program Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.7 Data Polling flag (DQ7 7.8 Toggle flag (DQ6) ...

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... PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 67 16.3 MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 16.4 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16.5 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 16.6 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 16.7 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 17.1 General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 17.2 Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 17.3 MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4/120 Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 17.4 PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.5 Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17.6 Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.7 Data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.8 Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 17.9 JTAG in-system programming (ISP 17.10 Port configuration registers (PCR 17.11 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17.12 Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17.13 Drive Select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 17.14 Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17 ...

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... Programming in-circuit using the JTAG/ISP interface . . . . . . . . . . . . . 95 20.1 Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 20.2 JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 20.3 Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 21 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 23 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 24 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V List of tables Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2. PLD I Table 3. JTAG signals on port Table 4. Methods for programming different functional blocks of the PSD Table 5. Register address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6. Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 7. Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 8. Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 9. DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 10 ...

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... List of tables Table 49. LQFP80 - 80-lead plastic thin, quad, flat package mechanical data 116 Table 50. PSD835G2V LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 51. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V List of figures Figure 1. LQFP80 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 2. PSD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. PSDsoft development tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4. Example for Flash Sector Chip Select FS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 5. Selecting the upper or lower block in a primary Flash memory sector . . . . . . . . . . . . . . . . 34 Figure 6. Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7. Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 8 ...

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... List of figures Figure 49. LQFP80 - 80 lead thin, quad, flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 1 Description The PSD family of memory systems for microcontrollers (MCUs) brings in-system- programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications. The CPLD in the PSD devices features an optimized macrocell logic architecture. The PSD macrocell was created to address the unique requirements of embedded system designs ...

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... PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro. 12/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V Figure 1. LQFP80 connections PD2 1 PD3 2 AD0 3 AD1 4 AD2 5 AD3 6 AD4 7 GND AD5 10 AD6 11 AD7 12 AD8 13 AD9 14 AD10 15 AD11 16 AD12 17 AD13 18 AD14 19 AD15 20 Doc ID 10585 Rev 3 Description 60 CNTL1 59 CNTL0 58 PA7 57 PA6 56 PA5 55 PA4 54 PA3 53 PA2 52 PA1 51 PA0 50 GND 49 GND 48 PC7 47 PC6 ...

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... Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs as input. Active low input. Resets I/O ports, PLD macrocells and some of the Configuration registers and JTAG registers. Must be low at Power-up. Reset also aborts the Flash programming/erase cycle that is in progress. Doc ID 10585 Rev 3 Description PSD835G2V ...

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... PSD835G2V Table 1. Pin description (continued) Pin Pin Type name PA0 58 PA1 57 PA2 56 I/O CMOS PA3 55 or Open PA4 54 Drain PA5 53 PA6 52 PA7 51 PB0 68 PB1 67 PB2 66 I/O CMOS PB3 65 or Open PB4 64 Drain PB5 63 PB6 62 PB7 61 PC0 48 PC1 47 PC2 46 I/O CMOS PC3 ...

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... PF0 through PF7 pins of port F. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. Input to the PLDs. Latched address outputs. As address A0-A3 inputs in 80C51XA mode. As data bus port (D07) in non-multiplexed bus configuration. Doc ID 10585 Rev 3 Description PSD835G2V ...

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... PSD835G2V Table 1. Pin description (continued) Pin Pin Type name 8, 30, I/O CMOS PG0-PG7 49, 50, or Open 70 Drain 9, 29 30, GND 49, 50, 70 PG0 through PG7 pins of port G. This port pins can be configured to have the following functions: MCU I/O – write to or read from a standard output or input port. ...

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... Description Figure 2. PSD block diagram 18/120 Doc ID 10585 Rev 3 PSD835G2V AI05793c ...

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... PSD835G2V 2 PSD architectural overview PSD devices contain several major functional blocks. the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. 2.1 Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled 4 Mbit (512K x 8) Flash memory is the primary memory of the PSD ...

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... Using the JTAG signals on port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. 20/120 Name Inputs 82 82 TMS TCK TDI TDO TSTAT TERR Table 3: JTAG signals on port E Doc ID 10585 Rev 3 PSD835G2V Outputs Product terms 150 JTAG signal indicates the ...

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... PSD835G2V 2.8 In-application reprogramming (IAP) The primary Flash memory can also be programmed in-system by the MCU executing the programming algorithms out of the secondary memory, or SRAM. Since this is a sizable separate block, the application can also continue to operate. The secondary memory can be programmed the same way by executing out of the primary Flash memory. The PLD or other PSD Configuration blocks can be programmed through the JTAG port or a device programmer ...

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... FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. 22/120 Figure 3. PSDsoft is available from our web site (the Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V Figure 3. PSDsoft development tool Choose MCU and PSD Automatically Configures MCU bus interface and other PSD Define PSD Pin and Node Functions Point-and-click definition of PSD pin functions, internal nodes and MCU system memory map Define General Purpose Logic in CPLD Point-and-click definition of combinatorial and registered logic in CPLD ...

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... Doc ID 10585 Rev 3 PSD835G2V Other Description (1) Reads port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to port pins, MCU I/O output mode Configures port pin as input or output Configures port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins ...

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... PSD835G2V Table 5. Register address offset (continued) Port Port Register name A B Page VM Memory_ID0 Memory_ID1 1. Other registers that are not part of the I/O ports. PSD register description and address offset Port Port Port Port Port Doc ID 10585 Rev 3 Other Description (1) E0 Page register ...

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... Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 Bit 5 Bit 4 Bit 3 Port pin 5 Port pin 4 Port pin 3 Doc ID 10585 Rev 3 PSD835G2V Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 Bit 1 Bit 0 Port pin 2 Port pin 1 Port pin 0 Bit 2 ...

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... PSD835G2V Drive registers – ports C, F Bit 7 Bit 6 Port pin 7 Port pin 6 Port pin <i> port pin <i> is configured for CMOS Output driver (default port pin <i> is configured in Slew Rate mode. Enable-Out registers – ports Bit 7 Bit 6 Port pin 7 Port pin 6 Port pin < ...

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... Sec4_Prot Sec3_Prot Read-only registers Bit 5 Bit 4 Bit 3 not used not used Sec3_Prot Bit 5 Bit 4 Bit 3 not used not used not used Doc ID 10585 Rev 3 PSD835G2V Bit 2 Bit 1 Bit 0 Mcella 2 Mcella 1 Mcella 0 Bit 2 Bit 1 Bit 0 Mcellb 2 Mcellb 1 Mcellb 0 Bit 2 Bit 1 Bit 0 Sec2_Prot ...

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... PSD835G2V JTAG_Enable 1 = JTAG port is enabled JTAG port is disabled. Page register Configure Page input to PLD. Default is PGR7-PGR0=00. Bit 7 Bit 6 PGR 7 PGR 6 PMMR0 register Bit 7 Bit 6 not used not used (set to ’0’) (set to ’0’) The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers ...

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... SRAM size is 16 Kbit 3h = SRAM size is 64 Kbit 30/120 Bit 5 Bit 4 Bit 3 not used FL_data Boot_data (set to ’0’) Bit 5 Bit 4 Bit 3 S_size 1 S_size 0 F_size 3 Doc ID 10585 Rev 3 PSD835G2V Bit 2 Bit 1 Bit 0 FL_code Boot_code SR_code Bit 2 Bit 1 Bit 0 F_size 2 F_size 1 F_size 0 ...

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... PSD835G2V Memory_ID1 register Bit 7 Bit 6 not used not used (set to ’0’) (set to ’0’) B_size[3: There is no secondary NVM 2h = Secondary NVM size is 256 Kbit B_type[1: Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM Bit 5 Bit 4 Bit 3 B_type 1 B_type 0 B_size 3 Doc ID 10585 Rev 3 ...

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... Secondary Flash memory Sector Setor size Select (Kbytes) signal 64 FS0 8 64 FS1 8 64 FS2 8 64 FS3 8 64 FS4 64 FS5 64 FS6 64 FS7 512 8 sectors 32 Doc ID 10585 Rev 3 PSD835G2V SRAM Sector SRAM SRAM size Select Select (Kbytes) signal signal CSBOOT0 16 RS0 CSBOOT1 CSBOOT2 CSBOOT3 4 sectors 16 ...

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... Upper and lower block in main Flash sector The PSD835G2V main Flash memory has eight 64-Kbyte sectors. The 64-Kbyte sector size may cause some difficulty in code mapping for an 8-bit MCU with only 64-Kbyte address space. To resolve this mapping issue, the PSD835G2V provides additional logic (see ...

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... A15 input to the primary Flash memory FLASH MEMORY CHIP SELECT PINS FS0-FS7 FA15 ADDR A15 MUX A15 NVM CONTROL BIT (1) A14-A0 Doc ID 10585 Rev 3 PSD835G2V PRIMARY FLASH MEMORY SECTOR ai07652 ai07653 ...

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... PSD835G2V Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). (1)(2)(3) Table 7. Instructions FS0-FS7 or CSBOOT0- Instruction CSBOOT3 (4) (5) Read 1 Read Primary 1 (6)13) Flash ID Read Sector 1 (6)(7)(8) Protection Program a Flash 1 (13) Byte ...

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... The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 12. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 13. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 36/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 7 Instructions An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes is properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations ...

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... The status bits can be read as for details. DQ7 DQ6 DQ5 DQ4 Data Toggle Error X Polling flag flag Doc ID 10585 Rev 3 PSD835G2V 7). The MCU can read the 7). The identifier for the device Table 7). The READ DQ3 DQ2 DQ1 DQ0 Erase Time out ...

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... PSD835G2V 7.7 Data Polling flag (DQ7) When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the complement of the bit being entered for programming/writing on the DQ7 bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling flag bit (DQ7 READ operation). ● ...

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... Sector Erase instructions. The Erase Time-out flag bit (DQ3) is reset to ’0’ after a Sector Erase cycle for a time period of 100 µs + 20% unless an additional Sector Erase instruction is decoded. After this time period, or when the additional Sector Erase instruction is decoded, the Erase Time-out flag bit (DQ3) is set to '1.' 40/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 8 Programming Flash memory Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. A Flash memory sector is erased to all 1s (FFh), and is programmed by setting selected bits to '0.' Although Flash memory is erased by-sector programmed Word-by-Word. The primary and secondary Flash memories require the MCU to send an instruction to ...

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... Erase cycle is complete the Error flag bit (DQ5) 42/120 START READ DQ5 & DQ7 at VALID ADDRESS DQ7 YES = DATA NO NO DQ5 = 1 YES READ DQ7 DQ7 YES = DATA NO FAIL PASS AI01369B Figure 7 shows the Data Toggle algorithm. Figure 7 Doc ID 10585 Rev 3 PSD835G2V Figure 7). still applies. the Toggle ...

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... PSD835G2V indicates a time-out condition on the Erase cycle; a ’0’ indicates no error. The MCU can read any location within the sector being erased to get the Toggle flag bit (DQ6) and the Error flag bit (DQ5). PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms. ...

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... Sector Erase is accepted only during an Erase cycle and defaults to READ mode. A 44/120 Table 7. If any byte of the Bulk Erase instruction is memory. The Error flag bit (DQ5) returns a ’1’ if there has been an memory. Doc ID 10585 Rev 3 PSD835G2V Section 8: Table 7. Additional Table 7). This allows reading of data ...

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... PSD835G2V Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle flag bit (DQ6) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle flag bit (DQ6) stops toggling between 0.1 µ ...

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... Flash memory is always ready for the MCU to fetch the bootstrap instructions after the Reset cycle is complete. 46/120 and Section : Flash Boot Protection Doc ID 10585 Rev 3 PSD835G2V Section : Flash Memory register). Table 7). It can also be Section 19.1: Power-Up ...

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... PSD835G2V 11 SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is high. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. SRAM Select (RS0) is configured using PSDsoft Express configuration. Doc ID 10585 Rev 3 SRAM 47/120 ...

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... Boot-up, and secondary Flash memory in the program space at Boot-up, and later swap the primary and secondary Flash memories. This is easily done with the VM register by using PSDsoft to configure it for Boot-up and having the MCU change it when desired. 48/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V Section : VM register Figure 8. Priority level of memory and I/O components 12.3 Configuration modes for MCUs with separate program and data spaces 12.3.1 Separate space modes Program space is separated from data space. For example, Program Select Enable (PSEN, CNTL2) is used to access the program code from the primary Flash memory, while Read Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and I/O port blocks ...

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... Sector Select and SRAM Select Figure 10. 8031 memory modules – combined space DPLD RD VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 50/120 Primary RS0 Flash Memory CSBOOT0-3 FS0-FS7 CS OE Doc ID 10585 Rev 3 PSD835G2V Secondary SRAM Flash Memory AI02870C ...

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... PSD835G2V 13 Page register The 8-bit Page register increases the addressing capability of the MCU by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations ...

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... The 8-bit Read-only Memory Status registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and ID1 registers. The contents of the registers are defined in and Section : Memory_ID1 52/120 register. Doc ID 10585 Rev 3 PSD835G2V Section : Memory_ID0 register ...

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... PSD835G2V 15 PLDs The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The ...

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... DPLD and CPLD inputs (continued) Input source Port F inputs Page register Macrocell A feedback Macrocell B feedback Secondary Flash memory Program Status bit 1. The address inputs are A19-A4 in 80C51XA mode. 54/120 Input name PF7-PF0 PGR7-PGR0 MCELLA.FB7-FB0 MCELLB.FB7-FB0 Ready/Busy Doc ID 10585 Rev 3 PSD835G2V Number of signals ...

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... PSD835G2V Figure 12. PLD diagram PORTS I/O BUS INPUT PLD Doc ID 10585 Rev 3 PLDs 55/120 ...

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... Additional address lines can be brought into PSD via port 56/120 Figure 13, is used for decoding the address for internal and external (INPUTS) (32) (8) (8) (8) (16) (4) (1) (3) (1) (1) Doc ID 10585 Rev 3 PSD835G2V CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT FS0 3 FS1 3 FS2 3 ...

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... PSD835G2V 15.3 Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to port D. ...

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... PLDs Figure 14. Macrocell and I/O port BUS INPUT PLD 58/120 MUX MUX ARRAY AND BUS INPUT PLD Doc ID 10585 Rev 3 PSD835G2V MUX MUX ...

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... PSD835G2V 15.4 Output macrocell (OMC) Eight of the output macrocells (OMC) are connected to port A pins and are named as McellA0-McellA7. The other eight macrocells are connected to port B pins and are named as McellB0-McellB7. The output macrocell (OMC) architecture is shown in there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other output macrocells (OMC) ...

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... The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction register output. The pin is enabled upon Power- output enable equation is defined and if the pin is declared as a PLD output in PSDsoft. 60/120 Section 17: I/O ports). The flip-flops in each of the 16 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V If the Output macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. Figure 15. CPLD output macrocell ...

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... Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and Slave_CS. 62/120 Figure Doc ID 10585 Rev 3 PSD835G2V 16. The input macrocells (IMC) Section 17: I/O ports. Figure 17 ...

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... PSD835G2V Figure 16. Input macrocell ARRAY AND BUS INPUT PLD Doc ID 10585 Rev 3 PLDs 63/120 ...

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... PLDs Figure 17. Handshaking communication using input macrocells 64/120 Doc ID 10585 Rev 3 PSD835G2V ...

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... PSD835G2V 15.10 External chip The CPLD also provides eight Chip Select outputs that can be used to select external devices. The Chip Selects can be routed to either port C or port F, depending on the pin declaration in the PSDsoft. Each Chip Select (ECS0-ECS7) consists of one product term that can be configured active high or low ...

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... WR RD PSEN ( PSEN (2) (2) WR PSEN ( PSEN (2) ( (2) (2) R/W E (2) ( (2) R/W E DBE (2) ( (2) (2) R/W DS (2) (2) R/W DS (2) (2) R/W E Doc ID 10585 Rev 3 PSD835G2V (1) PD0 ADIO0 PA3-PA0 PA7-PA4 (2) ALE A0 ALE A4 A3-A0 (2) ALE A0 (2) ALE A0 (2) ALE (2) A0 D3-D0 D7- ALE A0 D3-D0 D7-D4 (2) (2) (2) (2) ...

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... PSD835G2V 16.1 PSD interface to a multiplexed 8-bit bus Figure 19 shows an example of a system using a MCU with an 8-bit multiplexed bus and a PSD. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/AS, PD0) latches the address signals internally. Latched addresses can be brought out to port E, For G ...

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... Figure 20. An example of a typical 8-bit non-multiplexed bus interface MCU D7-D0 A15- BHE ALE RESET 68/120 22, Figure 23, and Figure 24 show examples of the basic connections PSD ADIO PORT WR ( CNTRL0 ) RD ( CNTRL1 ) BHE ( CNTRL2 ) RST ALE ( PD0 ) PORT D Doc ID 10585 Rev 3 PSD835G2V D7-D0 PORT F PORT G PORT A23-A16 A, B (OPTIONAL AI02879D ...

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... PSD835G2V 16.4 80C31 Figure 21 shows the bus interface for the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O ports blocks. ...

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... CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2 Doc ID 10585 Rev 3 PSD835G2V Page mode Non-Page mode, 80C31 compatible A7-A0 multiplex with D7-D0 Non-Page mode A7-A0 multiplex with D7-D0 Page mode A15-A8 multiplex with D7-D0 Page mode A15-A8 multiplex with D7-D0 ...

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... PSD835G2V Table 13. Interfacing the PSD with the 80C251, with one READ Input 80C31 U1 2 P1.0 P0.0 3 P1.1 P0.1 4 P1.2 P0.2 5 P1.3 P0.3 6 P0.4 P1.4 7 P1.5 P0.5 8 P0.6 P1.6 9 P0.7 P1.7 P2 P2.1 P2.2 CRYSTAL P2 P2.4 P2.5 P2.6 P2.7 WR RD/A16 PSEN 10 RESET RESET ...

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... A11 17 28 A12 29 A13 18 30 A14 19 31 A15 PSEN 33 ALE RESET Doc ID 10585 Rev 3 PSD835G2V A15-A8 AD7-AD0 V CC PSD (2) ADIO0 PF0 32 ADIO1 PF1 33 ADIO2 PF2 34 ADIO3 PF3 35 PF4 ADIO4 36 ADIO5 PF5 37 PF6 ADIO6 38 PF7 ADIO7 21 ADIO8 PG0 22 ADIO9 PG1 23 ADIO10 ...

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... PSD835G2V 16.6 80C51XA The Philips 80C51XA MCU family supports 16-bit multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits (D7-D0) ...

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... PB0 A9 41 PB1 A10 40 PB2 A11 39 PB3 A12 38 PB4 A13 37 PB5 A14 36 PB6 A15 35 PB7 6 R/W R RESET RESET RESET Doc ID 10585 Rev 3 PSD835G2V A15- 15:8] AD7-AD0 PSD (2) ADIO0 PF0 4 32 ADIO1 PF1 33 5 ADIO2 PF2 6 34 ADIO3 PF3 7 35 PF4 ADIO4 36 ...

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... PSD835G2V 17 I/O ports There are seven programmable I/O ports: ports and F. Each of the ports is eight bits except for port D, which is 4 bits. Each port pin is individually user-configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the MCU writing to on-chip registers in the CSIOP space ...

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... DATA OUT REG ADDRESS D ALE G MACROCELL OUTPUTS EXT CS READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT 76/120 DATA OUT Q ADDRESS Q DATA Doc ID 10585 Rev 3 PSD835G2V Table 17 shows how and PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL AI02885 ...

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... PSD835G2V 17.3 MCU I/O mode In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in A port pin can be put into MCU I/O mode by writing a ’ ...

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... Selected for MCU N/A with non-mux bus Declare pins only 1 Declare pins or logic equations for input N/A macrocells Logic equations N/A (PSEL0 & 1) Declare pins only N/A Doc ID 10585 Rev 3 PSD835G2V Port D Port E Port F Yes (A7- Yes (A7- No A0) A0) Yes No Yes No No Yes ...

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... PSD835G2V Table 16. I/O port latched address output assignments MCU 8051XA 80C251 (Page mode) All Other 8-Bit Multiplexed 8-Bit Non-Multiplexed Bus 1. N/A = Not Applicable 17.6 Address In mode For MCUs that have more than 16 address signals, the higher addresses can be connected to port and are routed as inputs to the PLDs. The address input can be latched in the Input macrocell (IMC) by Address Strobe (ALE/AS, PD0) ...

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... The direction of data flow for ports and F are controlled not only by the 80/120 PSEL DATA BUS Table 5. The addresses in Table 17, are used for setting the port show the port Architecture diagrams for ports A/B/C and E/F/G, Doc ID 10585 Rev 3 PSD835G2V PF0 - PF7 AI02886b interface. Table 5 are the offsets in Table 17 is 00h. ...

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... PSD835G2V direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction register has sole control of a given pin’s direction. An example of a configuration for a port with the three least significant bits set to output and ...

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... Rate Rate Open Open Open Drain Drain Drain Table 22, are used by the MCU to write data to or read Table 22 shows the register name, the ports having each register type, Doc ID 10585 Rev 3 PSD835G2V Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit 1 Open Open Open ...

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... PSD835G2V 17.17 Output macrocells (OMC) The CPLD output macrocells (OMC) occupy a location in the MCU’s address space. The MCU can read the output of the output macrocells (OMC). If the OMC Mask register bits are not set, writing to the macrocell loads data to the macrocell flip-flops (see PLDs) ...

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... Figure 27. Port A, B and C structure DATA OUT D WR MCELLA7-MCELLA0 (PORT A) MCELLB7-MCELLB0 (PORT B) EXT.CS (PORT C) READ MUX DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT 84/120 REG. DATA OUT DATA Doc ID 10585 Rev 3 PSD835G2V PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT INPUT MACROCELL AI02887b ...

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... PSD835G2V 17.22 Port D – functionality and structure Port D has four I/O pins. It can be configured to program one or more of the following functions (see Figure – MCU I/O mode – CPLD Input – direct input to CPLD, no Input macrocell (IMC). Port D pins can be configured in PSDsoft as input pins for other dedicated functions: ● ...

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... Port G can be configured to perform one or more of the following functions: ● MCU I/O mode ● Latched Address Out – Provide latched address out per ● Open Drain – pins can be configured in Open Drain mode. 86/120 mode. Doc ID 10585 Rev 3 PSD835G2V Table 26: Status during Power- Table 26. ...

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... PSD835G2V Figure 29. Port structure DATA OUT REG ADDRESS D ALE G EXT.CS (PORT F) READ MUX CONTROL REG DIR REG ENABLE PRODUCT TERM ( .OE ) DATA OUT Q ADDRESS Q A7-A0 OR A15-A8 DATA CPLD-INPUT ISP (PORT E) Doc ID 10585 Rev 3 PORT PIN OUTPUT MUX OUTPUT SELECT ENABLE OUT CONFIGURATION ...

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... Power management 18 Power management The PSD835G2V offers configurable power saving options. These options may be used individually or in combinations, as follows: ● All memory blocks in a PSD (primary and secondary Flash memory, and SRAM) are built with Power Management technology. In addition to using special silicon design methodology, power management technology puts the memories into standby mode when address/data inputs are not changing (zero DC current) ...

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... PSD835G2V 18.1 Automatic Power-down (APD) unit and Power-down mode The APD Unit, shown in activity of Address Strobe (ALE/AS, PD0). If the APD Unit is enabled, as soon as activity on Address Strobe (ALE/AS, PD0) stops, a four-bit counter starts counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN (PD1), Power-down (PDN) goes high, and the PSD enters Power-down mode, as discussed next ...

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... Memory Access recovery time delay access time to normal access (1) No Access PD for a bit definition of the two registers). Section 22: DC and AC parameters Doc ID 10585 Rev 3 PSD835G2V SECONDARY FLASH SELECT PRIMARY FLASH SELECT PLD SRAM SELECT POWER DOWN ( PDN ) SELECT AI02891b typical standby ...

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... PSD835G2V 18.4 PSD Chip Select Input (CSI, PD2) PD2 of port D can be configured in PSDsoft as the PSD Chip Select Input (CSI). When low, the signal selects and enables the internal (primary) Flash memory, secondary Flash memory, SRAM, and I/O blocks for READ or WRITE operations involving the PSD. A high on PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash memory, and SRAM, and reduces the PSD power consumption ...

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... PMMR2. Table 25. APD counter operation APD Enable bit 92/120 ALE PD ALE Level Polarity X X Not counting X Pulsing Not counting 1 1 Counting (generates PDN after 15 clock cycles Counting (generates PDN after 15 clock cycles) Doc ID 10585 Rev 3 PSD835G2V APD counter ...

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... PSD835G2V 19 Reset timing and device status at Reset 19.1 Power-Up Reset Upon Power-up, the PSD requires a Reset (RESET) pulse of duration t minimum) after V clears some of the registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in the Reset mode for an additional period, t (120ns maximum), before the first memory access is allowed ...

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... Power-Un Reset Warm Reset Unchanged Depends on .re and .pr equations Initialized, based on the selection in PSDsoft Configuration menu Cleared to ’0’ Doc ID 10585 Rev 3 PSD835G2V Power-down mode Unchanged Depends on inputs to PLD (addresses are blocked in PD mode) Not defined Tri-stated Tri-stated Power-down mode Unchanged Depends on ...

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... PSD835G2V 20 Programming in-circuit using the JTAG/ISP interface The JTAG/ISP Interface block can be enabled on port E (see (primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may be programmed through the JTAG/ISP Interface block. A blank device can be mounted on a printed circuit board and programmed using JTAG/ISP. ...

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... The Sector Protect bits can be set in PSDsoft. Table 27. JTAG port signals Port E pin PE0 PE1 PE2 PE3 PE4 PE5 96/120 JTAG signals TMS TCK TDI TDO TSTAT TERR Doc ID 10585 Rev 3 PSD835G2V Section 6.5: Description Mode Select Clock Serial Data In Serial Data Out Status Error flag ...

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... PSD835G2V 21 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied ...

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... In the PLD timing parameters, add the required delay when Turbo bit is '0.' Figure 33. PLD I 98/120 Figure 33 shows the PLD mA/MHz as a function of the number of Product /frequency consumption HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) Doc ID 10585 Rev 3 PSD835G2V PT 100 AI07656 ...

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... PSD835G2V Table 29. Example of PSD typical power calculation at V Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash memory Access = 80% % SRAM access % I/O access Operational modes % Normal % Power-down mode Number of product terms used (from fitter report total product terms ...

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... Freq ALE + % PLD x (from graph using Freq PLD µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 15 mA µA + 0.1 x (3.84 + 0. µA + 0.1 x 18. µ 1.98mA Doc ID 10585 Rev 3 PSD835G2V = 3.0V (with Turbo mode Off) (ac (dc ...

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... PSD835G2V Table 31. Operating conditions Symbol V Supply voltage CC Ambient operating temperature (industrial Ambient operating temperature (commercial) Table 32. AC signal letters for PLD timing 1. Example Time from Address Valid to ALE Invalid. AVLX Table 33. AC signal behavior symbols for PLD timing Symbol Example Time from Address Valid to ALE Invalid. ...

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... Figure 35. AC measurement load circuit 102/120 Parameter (1) Parameter Test Condition OUT °C and nominal supply voltages. A 3.0V Test Point 0V 2.01 V 195 Ω Device Under Test (Including Scope and Jig Capacitance) Doc ID 10585 Rev 3 PSD835G2V Min. Max. Unit 30 pF (2) Typ Max. Unit 1.5V AI03103b AI03104b ...

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... PSD835G2V Figure 36. Switching waveforms – key Table 36. DC characteristics Symbol Parameter V Input high voltage IH V Input low voltage IL V Reset high level input voltage IH1 V Reset low level input voltage IL1 V Reset pin hysteresis HYS V (min) for Flash Erase and CC V LKO ...

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... WRITE/Erase Only Read only MHz MHz is valid at or below 0.2V –0. IH1 INPUT tER INPUT TO OUTPUT tPD Doc ID 10585 Rev 3 Min. Typ. Max 400 700 - Figure (5) - 1.5 2.0 - 0.8 1.5 is valid at or above 0. tEA AI02863 PSD835G2V Unit mA µA/ mA/MHz mA/MHz AI07655 ...

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... PSD835G2V Table 37. CPLD combinatorial timing Symbol Parameter CPLD input pin/feedback CPLD combinatorial output CPLD input to CPLD output t EA enable CPLD input to CPLD output t ER disable CPLD register clear or preset t ARP delay CPLD register clear or preset t ARPW pulse Width t CPLD array delay ARD 1 ...

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... Figure 39. Synchronous clock mode timing – PLD REGISTERED OUTPUT 106/120 -90 Conditions Min Max 1/( 23.8 SA COA 1/(t +t –10) - 31.25 SA COA 1/( 38.4 CHA CLA Any macrocell - 23 1 CNTA t CH CLKIN INPUT Doc ID 10585 Rev 3 PSD835G2V -12 Turbo Slew PT aloc Off Rate Min Max - ...

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... PSD835G2V Figure 40. Asynchronous Reset / Preset RESET/PRESET REGISTER Figure 41. Asynchronous clock mode timing (product term clock) CLOCK REGISTERED OUTPUT Figure 42. Input macrocell timing (product term clock) PT CLOCK INPUT OUTPUT AI03101 Table 40. Input macrocell timing Symbol Parameter t Input setup time IS t Input hold time ...

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... AVLX t LXAX t LVLX ADDRESS VALID t AVQV ADDRESS VALID t SLQV t RLQV t RLRH t THEH ADDRESS OUT Conditions (1) (1) (1) (2) (3) (4) (4) (4) Doc ID 10585 Rev 3 PSD835G2V DATA VALID DATA VALID t RHQX tRHQZ t EHEL t ELTL AI02895 -90 -12 Turbo Off Min Max Min Max ...

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... PSD835G2V Table 41. READ timing (continued) Symbol Parameter t R/W setup time to Enable THEH t R/W hold time after Enable ELTL Address input valid to address output t AVPV delay 1. Any input used to select an internal PSD function timing has the same timing as DS signal and PSEN have the same timing for 80C51. ...

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... In multiplexed mode, latched address generated from ADIO delay to address output on any port. 7. Assuming data is stable before active WRITE signal. 110/120 Conditions (1) (1) (1)(2) (2) (2) (2)(3) (2) (2) (2)(4) (2) (2)(5) (6) (2)(7) Doc ID 10585 Rev 3 PSD835G2V -90 -12 Unit Min Max Min Max ...

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... PSD835G2V Figure 45. Peripheral I/O Read timing ALE/ BUS CSI RD Table 43. Port F Peripheral Data mode Read timing Symbol Parameter Address valid to data t AVQV–PF valid t CSI valid to data valid SLQV– data valid t RLQV– data valid 8031 mode t Data In to data out valid DVQV– ...

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... Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 112/120 ADDRESS tWLQV (PF) Conditions Parameter (pre-programmed to “00”) (2) Doc ID 10585 Rev 3 PSD835G2V DATA OUT tWHQZ (PF) tDVQV (PF) PORT F DATA OUT -90 -12 Min Max Min ...

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... PSD835G2V Table 46. Power-down timing Symbol Parameter t ALE access time from Power-down LVDV Maximum delay from t CLWH APD Enable to internal PDN valid signal the period of CLKIN (PD1). CLCL Figure 47. Reset (RESET) timing V (min NLNH-PO Power-On Reset RESET Table 47. Reset (RESET) timing Symbol ...

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... ISC port high-impedance to valid output ISCPZV ISC port valid output to t ISCPVZ high-impedance 1. For non-PLD programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. 114/120 ISCCH t ISCCL t t ISCPSU ISCPH Conditions Doc ID 10585 Rev 3 PSD835G2V t ISCPZV t ISCPCO t ISCPVZ AI02865 -90 -12 Min Max Min ( (1) ...

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... PSD835G2V 23 Package mechanical In order to meet environmental requirements, ST offers this device in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Doc ID 10585 Rev 3 Package mechanical ® 115/120 ...

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... PSD835G2V 9X_ME (1) Max 0.0630 0.0060 0.0570 0.0110 0.0080 – – – – – – – 0.0300 – 7° 0.003 ...

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... PSD835G2V 24 Part numbering Ordering information scheme Example: Device type PSD8 = 8-bit PSD with register Logic SRAM size Kbit Flash memory size Mbit (512 Kb x8) I/O count I/O 2nd Flash memory 2 = 256 Kbit (32 Kb x8) Flash memory Operating voltage 3 Speed 120 ns ...

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... Pin assignments Appendix A Pin assignments Table 50. PSD835G2V LQFP80 Pin no. Pin assignments Pin no. Pin assignments Pin no. Pin assignments Pin no. Pin assignments 1 PD2 21 2 PD3 22 3 AD0 23 4 AD1 24 5 AD2 25 6 AD3 26 7 AD4 27 8 GND AD5 30 11 AD6 31 12 AD7 32 13 ...

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... PSD835G2V 25 Revision history Table 51. Document revision history Date 03-Mar-04 24-April-2007 05-May-09 Revision 1 Document reformatted: split from original with both voltage options. Document maturity promoted from Preliminary Data to full Datasheet. T removed from 2 LEAD Added ECOPACK text in Document reformatted. Notes modified in Updated note 1 below ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 120/120 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 10585 Rev 3 PSD835G2V ...