PSD835G2V-12U STMicroelectronics, PSD835G2V-12U Datasheet - Page 73

• Manufacturer Part Number: PSD835G2V-12U
• Manufacturer: STMicroelectronics

Specifications of PSD835G2V-12U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / Rohs Status: Compliant

PSD835G2V
16.6
Figure 23. Interfacing the PSD with the 80C51X, 8-bit data bus
RESET
CRYSTAL
RESET
80C51XA
The Philips 80C51XA MCU family supports an 8- or 16-bit multiplexed bus that can have
burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with
data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits
(D7-D0).
The 80C51XA can be configured to operate in eight-bit data mode (as shown in
The 80C51XA improves bus throughput and performance by executing burst cycles for code
fetches. In Burst mode, address A19-A4 are latched internally by the PSD, while the
80C51XA changes the A3-A0 signals to fetch up to 16 bytes of code. The PSD access time
is then measured from address A3-A0 valid to data in valid. The PSD bus timing
requirement in Burst mode is identical to the normal bus cycle, except the address setup
and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply.
V CC
15
35
14
10
21
20
11
13
16
6
7
9
8
INT0
INT1
XTAL1
XTAL2
RXD0
TXD0
RXD1
TXD1
RESET
EA/WAIT
T2EX
T2
T0
80C31
A0/WRH
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
A10D6
A11D7
A12D8
A13D9
PSEN
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
WRL
ALE
RD
A2
A3
A1
RESET
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
33
32
19
5
4
3
2
18
Doc ID 10585 Rev 3
A2
A0
A3
A1
PSEN
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
WR
A8
A9
A10
A11
A12
A13
A14
A15
RD
39
10
11
12
16
77
78
13
14
15
17
18
19
71
72
73
74
75
76
20
40
59
60
79
80
3
4
5
6
7
1
2
PSD
ADIO0
ADIO1
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PE6
PE7
ADIO2
PD0 (ALE)
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL2 (PSEN)
PD1 (CLKIN)
PD2 (CS)
PD3
RESET
GND GND GND GND GND
V CC
(2)
8
9
V CC
30
V CC
29
49
V CC
69
50
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
70
MCU bus interface
31
32
33
34
35
36
37
38
42
43
44
45
46
47
48
52
53
54
55
56
57
58
67
21
22
23
24
25
26
27
28
61
62
63
64
65
66
68
41
51
A [ 19:12 ] D[7:0]
A [3 :0 ]
Figure
AI02883e
73/120
23).