PSD835G2V-12U STMicroelectronics, PSD835G2V-12U Datasheet - Page 90

• Manufacturer Part Number: PSD835G2V-12U
• Manufacturer: STMicroelectronics

Specifications of PSD835G2V-12U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / Rohs Status: Compliant

Power management
Figure 30. APD unit
18.2
18.3
90/120
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
Table 24.
1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on
2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is '0.'
Other power saving options
The PSD offers other reduced power saving options that are independent of the Power-
down mode. Except for the SRAM Standby and Chip Select Input (CSI, PD2) features, they
are enabled by setting bits in the PMMR0 and PMMR2 registers (see
register
PLD Power Management
The power and speed of the PLDs are controlled by the Turbo bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified standby
current when the inputs are not switching for an extended time of 70ns. The propagation
delay time is increased after the Turbo bit is set to ’1’ (turned off) when the inputs change at
a composite frequency of less than 15 MHz. When the Turbo bit is reset to ’0’ (turned on),
the PLDs run at full power and speed. The Turbo bit affects the PLD’s DC power, AC power,
and propagation delay. Refer to
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
Power-
Mode
down
the Turbo bit.
DISABLE PRIMARY AND
SECONDARY FLASH/SRAM MEMORIES
and
TRANSITION
DETECTION
DETECT
EDGE
PLD propagation
Section : PMMR2 register
PSD timing and standby current during Power-down mode
Normal t
delay
PD
(1)
Doc ID 10585 Rev 3
access time
Section 22: DC and AC parameters
No Access
CLR
COUNTER
Memory
APD
PD
PD
for a bit definition of the two registers).
Access recovery time
DISABLE BUS
INTERFACE
to normal access
t
LVDV
PLD
SECONDARY FLASH SELECT
PRIMARY FLASH SELECT
POWER DOWN
( PDN )
SRAM SELECT
SELECT
for PLD timings.
Section : PMMR0
typical standby
5 V V
50 µA
current
PSD835G2V
CC
(2)
AI02891b