PSD835G2V-12U STMicroelectronics, PSD835G2V-12U Datasheet - Page 39

• Manufacturer Part Number: PSD835G2V-12U
• Manufacturer: STMicroelectronics

Specifications of PSD835G2V-12U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / Rohs Status: Compliant

PSD835G2V
7.7
7.8
7.9
Data Polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the
complement of the bit being entered for programming/writing on the DQ7 bit. Once the
Program instruction or the WRITE operation is completed, the true logic value is read on the
Data Polling flag bit (DQ7, in a READ operation).
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Toggle flag (DQ6)
The PSD offers another way for determining when the Flash memory Program cycle is
completed. During the internal WRITE operation and when either the FS0-FS7 or
CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to ’0’ on
subsequent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling stops and the data read on the Data Bus
D0-D7 is the addressed memory byte. The device is now accessible for a new READ or
WRITE operation. The cycle is finished when two successive READs yield the same output
data.
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Error flag (DQ5)
During a normal Program or Erase cycle, the Error flag bit (DQ5) is set to '0.' This bit is set to
’1’ when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase
cycle.
In the case of Flash memory programming, the Error flag bit (DQ5) indicates the attempt to
program a Flash memory bit from the programmed state, 0, to the erased state, 1, which is
not valid. The Error flag bit (DQ5) may also indicate a Time-out condition while attempting to
program a byte.
In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash
memory sector in which the error occurred or to which the programmed byte belongs must
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after
the sixth WRITE pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
During an Erase cycle, the Data Polling flag bit (DQ7) outputs a '0.' After completion of
the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a ’1’ after
erasing).
If the byte to be programmed is in a protected Flash memory sector, the instruction is
ignored.
If all the Flash memory sectors to be erased are protected, the Data Polling flag bit
(DQ7) is reset to ’0’ for about 100 µs, and then returns to the previous addressed byte.
No erasure is performed.
The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for an Erase instruction).
If the byte to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit
(DQ6) toggles to ’0’ for about 100 µs and then returns to the previous addressed byte.
Doc ID 10585 Rev 3
Instructions
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