PSD835G2V-12U STMicroelectronics, PSD835G2V-12U Datasheet - Page 69

• Manufacturer Part Number: PSD835G2V-12U
• Manufacturer: STMicroelectronics

Specifications of PSD835G2V-12U

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: TQFP
• Mounting: Surface Mount
• Pin Count: 80
• Lead Free Status / Rohs Status: Compliant

PSD835G2V
16.4
Figure 21. Interfacing the PSD with an 80C31
CRYSTAL
RESET
RESET
80C31
Figure 21
address/data bus. The lower address byte is multiplexed with the data bus. The MCU control
signals Program Select Enable (PSEN, CNTL2), Read Strobe (RD, CNTL1), and Write
Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O ports blocks.
Address Strobe (ALE/AS, PD0) latches the address.
15
12
13
14
10
11
19
18
31
9
2
3
4
5
6
7
8
1
80C31
RXD
TXD
X1
X2
RESET
INT0
INT1
T0
T1
EA/VP
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
shows the bus interface for the 80C31, which has an 8-bit multiplexed
ALE/P
PSEN
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
RD
RESET
16
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
29
30
Doc ID 10585 Rev 3
RD
PSEN
WR
ALE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
A15
40
39
59
60
10
11
12
16
77
78
13
14
15
17
18
19
71
72
73
74
75
76
20
79
80
3
4
5
6
7
1
2
PSD
ADIO0
ADIO1
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
PE6
PE7
ADIO2
PD0 (ALE)
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1(RD)
CNTL2 (PSEN)
PD1 (CLKIN)
PD2 (CS)
PD3
RESET
AD7-AD0
GND GND GND GND GND
A15-A8
V CC
8
V CC
30
V CC
49
V CC
MCU bus interface
50
70
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA1
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PA2
31
32
33
34
35
36
37
38
52
53
54
55
56
57
58
67
42
43
44
45
46
47
48
27
61
62
63
64
65
66
68
41
21
22
23
24
25
26
28
51
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