PEF2054NV21XT Lantiq, PEF2054NV21XT Datasheet - Page 101

• Manufacturer Part Number: PEF2054NV21XT
• Manufacturer: Lantiq

Specifications of PEF2054NV21XT

• Lead Free Status / Rohs Status: Compliant

recommended to program the PCM loop in the control memory (refer to
chapter 5.4.3.1).
If OMDR:PTL is set to logical 1, the test loop is enabled i.e. the physical transmit pins
TxD# are internally connected to the corresponding physical receive pins RxD#, such
that data transmitted over TxD# are internally looped back to RxD# and data externally
received over RxD# are ignored. The TxD# pins still output the contents of the upstream
data memory according to the setting of the tristate field.
PCM Test Loop OMDR:PTL
The PCM test loop function can be used for diagnostic purposes if desired. If however a
“simple” CFI to CFI connection (CFI
Note: This loop back function can only work if the upstream and downstream bit shifts
For normal operation OMDR:PTL should be set to logical 0 (test loop disabled).
Figure 29 illustrates the effect of the PTL bit:
Figure 29
Effect of the OMDR:PTL Bit
Semiconductor Group
match and if the port assignment (PMOD:AIS1 … 0) is such that a logical
transmitter is looped back to a logical receiver (e.g. the PTL loop cannot work in
PCM mode 2!).
From Upstream
Data Memory
To Downstream
Data Memory
EPIC
R
PCM
101
OMDR PTL
:
1
ITS09546
0
CFI loop) shall be established, it is
PCM Interface
TxD#
RxD#
Application Hints
PEB 2055
PEF 2055